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  • Syllabus
    • Instructor
    • Instructional Format
    • Course Websites
    • Course Description
    • Examination Schedule
    • Expected Outcomes
    • Expected Background
    • Textbook and References
    • Course Work
    • Grading
    • Late Work Policy
    • Academic Integrity
    • Academic Accomodations
    • Diversity, Equity and Inclusion
    • Tentative Schedule
  • Lectures
    • ASIC Technology
    • System On Chip
    • SystemVerilog
    • RTL Synthesis
    • Timing Analysis
    • Design Flow
    • Digital IC Layout
    • Optimizing Area and Timing
    • Power Analysis and Optimization
    • Full-chip layout
  • Labs
    • Area-Time Tradeoff in a Hardware Multiplier
    • A Coprocessor for the Bresenham Line-Drawing Algorithm
  • Project
    • Project: A hardware-accelerated MAC function
  • Project: A hardware-accelerated MAC function
    • Project Timeline
    • Reference Implementation
    • Project Definition Phase
    • Project Design Phase
    • Project Implementation Phase
    • Project Presentation
  • Resources
    • Verilog and SystemVerilog
    • Unix Command Line
Advanced Digital Systems Design Fall 2024
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