Attention

This document was last updated Nov 25 24 at 21:59

Syllabus

Instructor

Instructional Format

  • This class is organized as a flipped classroom. That means that the lecture materials will be posted before the lecture, and the class meeting time will be used for problem solving and clarifications of the course material. Lecture videos and materials will be available by Monday of every week.

  • This class is concurrently taught in two formats: asynchronous and synchronous. Students can be enrolled in either the asynchronous version or else the synchronous version of the course, but not both. The lecture materials and lecture videos are shared between the asynchronous and synchronous version of the course.

  • The student course work and interaction depends on the format of the course.

    • Students enrolled in the synchronous version of the course will meet on Wednesdays in AK 232 at 6PM. Class meeting time will be one hour by default, but can be adjusted depending on the discussions and course work at hand. If class meeting time extends beyond 7 PM, this will be clearly announced before the lecture.

    • Students enrolled in the asynchronous version of the course will interact asynchronously with the instructor through the canvas messaging system

Course Websites

Course Description

This course introduces digital systems design using hardware description languages and their associated tooling to capture, integrate, verify, simulate, and synthesize digital hardware. The course will examine modern hardware design flows using high-level synthesis and register-transfer-level (RTL) synthesis. The course covers the role of hardware description languages in the verification, simulation, and integration process of hardware modules in large digital systems. The course projects offer an integrated experience in advanced digital systems design combining hardware description languages, hardware design methodologies, and hardware design practice on a programmable target such as a Field Programmable Gate Array, or on a chip-level target such as a standard-cell Application-Specific Integrated Circuit. (Prerequisites: Basic digital design, Experience with programming in a high-level language).

Examination Schedule

Please note that this list only includes major deadlines; minor deadlines for hands-on assignments will be announced through canvas.

  • Lab 1 Due Date: Friday, 29 September

  • Lab 2 Due Date: Friday, 10 November

  • Project Report Due Date: Wednesday, 13 December

Expected Outcomes

Students who successfully complete this course should be able to:

  • describe the major steps of modern digital hardware design, including specification, design, verification, and integration.

  • evaluate the cost factors involved in digital hardware design including area, performance, power, and design effort.

  • trade-off and optimize the cost factors of digital hardware using manual refinement and automatic transformations.

  • apply design tools to support complex digital system design, including digital simulators, logic synthesis, high-level synthesis, and back-end technology mapping.

  • undertake a substantial design project that integrates every step of the digital design flow towards a concrete design objective.

  • express the design decisions and outcomes of complex digital design in a concise report.

Expected Background

Students taking ECE 574 should have a good understanding of basic digital logic design such as covered in ECE 2029 (Introduction to Digital Circuit Design). It’s also helpful, but not vital, to have knowledge on microelectronic circuit technology such as covered in ECE 2201 (Microelectronic Circuits I) and ECE 3204 (Microelectronic Circuits II). Finally, to hit the ground running, it helps to know about the digital design at the RTL level, such as covered in ECE 3829 (Advanced Digital System Design With FPGAs).

The course includes a substantial design project which requires the use of design automation tools for the implementation and verification of digital design for ASIC and/or FPGA. This will require hands-on programming in a suitable hardware description language (HDL) as well as the associated scripting and support used to set up a synthesis/ simulation/ verification flow.

Textbook and References

  • There is no set textbook for the course.

  • There will be assigned reading for the course, selected from articles and references posted by the instructor.

  • Students will receive an invitation from the Cadence University Program that grants access to the online support website for Cadence Tools. If you did not receive this email, please contact the instructor.

Course Work

The course includes hands-on assignments, lab assignments, and a course project.

  • The hands-on assignments are according to the topic of the week and may include an excercise, a short report, or a presentation. The assignment will be posted early in the week, and will be due by the beginning of the following week.

  • For students enrolled in the synchronous version of the course, the hands-on assignments can be completed in-class.

  • For students enrolled in the asynchronous version of the course, the hands-on assignmments can be completed at home after studying the online course materials for the week.

  • Hands-on assignments will be based in part on instructional materials by Cadence. Students will receive access to Cadence Online Learning and Support for the duration of the course.

  • The lab assignments will involve simulation/design excercises of digital logic. The lab assignments are individual exercises that must be solved in two weeks.

  • The course project is a multi-part assignment that involves the design, verification, and optimization of a digital hardware system. The final project can be solved in teams of 1 to 2 students. The final project includes multiple deliverables, including a preproposal document, a proposal document, a design document, a testing document, and an evaluation document.

  • For students enrolled in the synchronous version of the course, the final project requires an in-class presentation to summarize the findings at the end of the course. During the project, the students will have the opportunity to meet with the instructor.

  • For students enrolled in the asynchronous version of the course, the final project requires a recorded video to summarize the findings at the end of the course. During the project, the students will have the opportunity to meet with the instructor online.

  • Student Feedback: The instructor aims to provide timely feedback to student emails, quizzes (hands-on) and labs. Please allow the following minimum time windows: 24 hours for emails, 3 days for quizz (hands-on) feedback, 1 week for labs.

Grading

A small portion of your grade is for ‘class participation’. That includes any online activity that reflects your participation in the class such as attending, asking questions and posting questions on the bulletin board.

Course Work

Grade Weight

Hands-on Assignments

40% of the points

Lab 1

15% of the points

Lab 2

15% of the points

Course Project

30% of the points

Final course grades are based on a student’s performance as follows:

Letter Grade

Percentage

A

90 - 100

B

80 - 90

C

60 - 80

NR

< 60

Late Work Policy

Individual labs and team project submissions will be closed at the deadline unless an extension has been discussed with the instructor in advance of the deadline and authorized by the instructor in the form of a revised deadline. In other words - if you are late, you have to talk to the instructor.

Academic Integrity

You are expected to be familiar with the Student Guide to Academic Integrity at WPI. Consequences for violating the Academic Honest Policy range from earning a zero on the assignment, failing the course, or being suspended or expelled from WPI.

Common examples of violations include:

  • Copying and pasting text directly from a source without providing appropriately cited credit

  • Paraphrasing, summarizing, or rephrasing from a source without providing appropriate citations

  • Collaborating on individual assignments

  • Turning in work where a good portion of the work is someone else’s, even if properly cited

Keep in mind that some course work must be solved individually, and some coursework allows collaboration:

  • The labs and midterm are individual assignments, and no teamwork is allowed for those assignments.

  • The course project can be solved as a team (1-2 students). Every student on the team will earn the same grade for the project. For the purpose of Academic Integrity, all members of a project team are considered as a single person.

Academic Accomodations

Students with approved academic accommodations should plan to submit their accommodation letters through the Office of Accessibility Services Student Portal. Should you have any questions about how accommodations can be implemented in this particular course, please contact me as soon as possible. Students who are not currently registered with the Office of Accessibility Services (OAS) but who would like to find out more information about requesting accommodations, documentation guidelines, and what the accommodated interactive process entails should plan to contact OAS either by email AccessibilityServices@wpi.edu, by phone (508) 831-4908, or by stopping by the office on the 5th floor of Unity Hall.

Tentative Schedule

Week

Class

Topics

Lab

Tool

Week 1

W 8/28

ASIC Technology

Week 2

W 9/4

System On Chip

IBEX

Week 3

W 9/11

SystemVerilog

Lab 1

Xcelium

Week 4

W 9/18

RTL Synthesis

Genus

Week 5

W 9/25

Timing Analysis

Tempus

Week 6

W 10/2

Design Flows

Lab 1 Due

Week 7

W 10/9

Floorplanning

Innovus

Week 8

W 10/23

Optimizing Area and Timing

Lab 2

Week 9

W 10/30

Optimizing Power

Joules

Week 10

W 11/6

Layout Finishing

Lab 2 Due

Week 11

W 11/13

Project Definition

Week 12

W 11/20

Project Design

Week 13

W 12/4

Project Implementation

Week 14

W 12/11

Project Presentation