Attention
This document was last updated Nov 25 24 at 21:59
Digital IC Layout
Important
The purpose of this lecture is as follows.
To describe the major steps in transforming a gate-level netlist into an IC layout
To identify the inputs and outputs of each design step
To demonstrate an place-and-route tool that constructs layout
To demonstrate gate-level simulation and gate-level state timing analysis
Attention
The following references are relevant background to this lecture.
Stok, D. Hathaway, K. Keutzer, D. Chinnery, ‘Design Flows,’ Chapter 1 in “EDA for IC Implementation, Circuit Design and Process Technology,” Taylor and Francis 2006.
Kahng, J. Lienig, I. L. Markov, J. Hu, “VLSI Physical Design,” Springer 2011.
Please refer to Canvas for links to relevant background reading