.. ECE 574

.. attention::

   This document was last updated |today|

.. _07layout:

Digital IC Layout
=================

.. important::

   The purpose of this lecture is as follows.

   * To describe the major steps in transforming a gate-level netlist into an IC layout
   * To identify the inputs and outputs of each design step
   * To demonstrate an place-and-route tool that constructs layout
   * To demonstrate gate-level simulation and gate-level state timing analysis

.. attention::

   The following references are relevant background to this lecture.

   * L. Stok, D. Hathaway, K. Keutzer, D. Chinnery, 'Design Flows,' Chapter 1 in "EDA for IC Implementation, Circuit Design and Process Technology," Taylor and Francis 2006.

   * A. Kahng, J. Lienig, I. L. Markov, J. Hu, "`VLSI Physical Design <https://link.springer.com/book/10.1007/978-90-481-9591-6>`_," Springer 2011.


Please refer to Canvas for links to relevant background reading