Syllabus
Instructor
Instructional Format
Course Websites
Course Description
Examination Schedule
Expected Outcomes
Expected Background
Textbook and References
Course Work
Grading
Late Work Policy
Academic Integrity
Academic Accomodations
Diversity, Equity and Inclusion
Tentative Schedule
Lectures
ASIC Technology
SystemVerilog
Simulation
RTL Synthesis
Arithmetic
Timing Analysis
Digital IC Layout
Optimizing Area and Timing
Power Analysis and Optimization
Full-chip layout
Labs
Area-Time Tradeoff in a Hardware Multiplier
Optimized 32-bit CORDIC Module for GPDK45
Project
Project Timeline
Project Phases
Grading
Advanced Digital Systems Design Fall 2023
Index
Index