Advanced Digital Systems Design - ECE 574

Course Summary

This course introduces digital systems design using hardware description languages and their associated tooling to capture, integrate, verify, simulate, and synthesize digital hardware. The course will examine modern hardware design flows using high-level synthesis and register-transfer-level (RTL) synthesis. The course covers the role of hardware description languages in the verification, simulation, and integration process of hardware modules in large digital systems. The course projects offer an integrated experience in advanced digital systems design combining hardware description languages, hardware design methodologies, and hardware design practice on a programmable target such as a Field Programmable Gate Array, or on a chip-level target such as a standard-cell Application-Specific Integrated Circuit. (Prerequisites: Basic digital design, Experience with programming in a high-level language).

Rationale

40 years ago, the world of chip design was profoundly affected by the publication of the book ‘Introduction to VLSI systems’ by Carver Mead and Lynn Conway. The book was based upon a course they taught at Caltech, Berkeley and MIT. Up until then, integrated circuit design was an ad-hoc process, and it was commonly taught as ‘drawing layouts’ in which a chip is directly developed at the lowest level of abstraction (physical polygons), and in which the chip design is completed by technology experts. The Mead and Conway book was insightful in pointing out that chip design is more than drawing layouts; namely that there are higher level concepts such as controllers, data paths, circuit timing, synchronous computation, that strongly influence the quality of the resulting chip. Our present day thinking on VLSI Design is still strongly influenced by the concepts of Mead and Conway’s textbook.

Similarly, we see that the world of hardware design is undergoing rapid innovation as well. The original concept of Verilog/VHDL hardware design, stems from the mid 80’s, and represents a traditional vision on hardware design: rigid, bottom-up, technology specific, incapable of integration. But in 2022, hardware design has moved on. While Verilog and VHDL are still the primary means to get from a textual representation of hardware to a digital chip implementation, there are many aspects in hardware design that are no longer adequately captured with Verilog and VHDL based methodologies.

To address the changing world of hardware design, ECE 574 brings innovation in two areas: first, in hardware modeling, and second, in hardware abstraction. Regarding the first area, there are a great number of innovative hardware modeling techniques that have been proposed (and that are in industrial use) to address specific challenges related to hardware system testing, hardware system prototyping, and to handling design complexity. While Verilog/VHDL will remain a centerpiece of the revised 574 course, it is essential to relate the traditional hardware modeling techniques to new efforts (SystemVerilog, UVM, Chisel, PyHDL, …). Regarding the second area, even though Verilog/VHDL are said to support bottom-up and top-down design, digital design practice has stuck with bottom-up design. A sound hardware methodology must recognize the value and purpose of higher abstraction levels of modeling, and their use in a combined bottom-up, top-down process. Hardware modeling techniques must cover multiple levels of abstraction, and they must be compatible with non-hardware artifacts such as processors and system simulation environments.