Sponsors
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Projects
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National Science Foundation Award 2434157 NSF-DFG: SaTC: CORE: Small: Demonstrating Practical Provable Side-channel Security Patrick Schaumont |
2025 - 2028 |
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Purdue Center for Secure Microelectronics Ecosystem Hierarchical Side-channel Leakage Assessment for Post Quantum Cryptographic Accelerators Patrick Schaumont |
2025 - 2028 |
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National Science Foundation Award 2346138 POSE: Phase I: An Open-Source Approach to Measure and Analyze Embedded Systems Security Patrick Schaumont, Fatemeh Ganji, Aydin Aysu |
2024 - 2025 |
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Office of Naval Research Sample Preparation for IC Security Assessment (DURIP) Patrick Schaumont, Shahin Tajik, Ulkuhan Guler |
2024 - 2025 |
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Meta Research Compromise-resistant secure hardware design Patrick Schaumont |
2022 - 2023 |
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National Science Foundation Award 2219810 Collaborative: FMitF: Track I: A Principled Approach to Modeling and Analysis of Hardware Fault Attacks on Embedded Software Patrick Schaumont |
2022 - 2026 |
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Massachusetts Technology Collaborative Grant 22030006-AWD Toward a Globaly Competitive Electronics Workforce Endowed with Next Generation CyberSecurity Technologies Shahin Tajik, Fatemeh Ganji, Patrick Schaumont, Berk Sunar |
2022 - 2023 |
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National Science Foundation Award 2117349 MRI: Acquisition of High-Resolution Photon Emission/Laser Fault Injection Microscope with High-Performance Computers for Failure Analysis and Security Assessment of Electronic Systems Fatemeh Ganji, Shain Tajik, Ulkuhan Guler, Patrick Schaumont, Berk Sunar |
2021 - 2024 |
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Intrinsix Inc (DARPA) Side Channel Attack Testbench Emulator (SCATE) Patrick Schaumont |
2020 - 2022 |
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CISCO CSR Grant PCBmeter: Remote PCB Verification using On-chip IP cores Shahin Tajik, Patrick Schaumont |
2020 - 2021 |
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Electric Power Research Institute Hardware Signature Testing Methodology for Standard PCB Patrick Schaumont, Shahin Tajik |
2020 - 2021 |
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Virginia Commonwealth University (INL) Towards a Safe and Secure-by-design Version of the SymPLE Architecture Carl Elks, Patrick Schaumont |
2019 - 2020 |
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National Science Foundation Award 2028190 RAPID: Collaborative: A privacy-preserving contact tracing system for COVID-19 containment and mitigation Yaling Yang, Patrick Schaumont |
2020 - 2021 |
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National Science Foundation Award 1931639 SaTC: CORE: Small: Finding and Mitigating Side-channel Leakage in Embedded Architectures Patrick Schaumont, William Diehl |
2019 - 2022 |
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National Institute of Standards and Technology Award 70NANB17H280 Efficiency of Logic Minimization Algorithms for Cryptographic Hardware Implementation Patrick Schaumont, Leyla Nazhandali |
2017 - 2019 |
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National Science Foundation Award 1704176 SaTC: CORE: Medium: Collaborative: Energy-Harvested Security for the Internet of Things Patrick Schaumont, Dong Ha, Chao Wang (USC) |
2017 - 2021 |
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Semiconductor Research Corporation Pre-computed Security Protocols for Energy Harvested IoT Patrick Schaumont |
2017 - 2019 |
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National Science Foundation Award 1617203 TWC: Small: Secure by Construction: An Automated Approach to Comprehensive Side Channel Resistance Chao Wang, Patrick Schaumont |
2016 - 2019 |
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Cisco CSR Grant Remote Device Integrity by Physical Proofs Patrick Schaumont |
2015 - 2016 |
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National Science Foundation Award 1441710 SaTC: STARSS: FAME: Fault-attack Awareness using Microprocessor Enhancements Patrick Schaumont, Leyla Nazhandali |
2014 - 2017 |
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ICTAS at Virginia Tech Synthesis of Software Countermeasures to Defend against Side-channel Attacks Chao Wang, Patrick Schaumont |
2014 - 2015 |
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National Science Foundation Award 1314598 TWC SBE: Medium: Collaborative: Dollars for Hertz: Making Trustworthy Spectrum Sharing Technically and Economically Viable Jung-Min Park, Patrick Schaumont |
2013 - 2017 |
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Intel Corporation Grant Embedded Systems Curriculum Patrick Schaumont |
2013 - 2014 |
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National Science Foundation Award 1115839 TC: Small: New Directions in Side Channel Attacks and Countermeasures Inyoung Kim, Patrick Schaumont |
2011 - 2014 |
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National Science Foundation Award 0964680 TC: Medium: From Statistics to Circuits: Foundations for Future On-chip Fingerprints Patrick Schaumont, Leyla Nazhandali, Inyoung Kim |
2010 - 2013 |
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National Science Foundation Award 0916763 NetSE: Cross-domain Design Tools for Sensor Network and Architecture Yaling Yang, Patrick Schaumont |
2009 - 2012 |
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National Science Foundation Award 0855095 II-NEW: Infrastructure to Collect and Analyze Circuit Variability in FPGAs Patrick Schaumont |
2009 - 2012 |
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National Institute for Standards and Technology Grant 60NANB10D004 Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software Kris Gaj (GMU), Jens-Peter Kaps (GMU), Patrick Schaumont, Leyla Nazhandali, Daniel Bernstein (UIC) |
2010 - 2012 |
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National Science Foundation Award 0644070 CAREER: Hardware/Software Codesign for Secure Embedded Systems: Methods and Education Patrick Schaumont |
2007 - 2011 |
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ICTAS at Virginia Tech Unique and Unclonable On-chip Identifiers Patrick Schaumont, Leyla Nazhandali, Inyoung Kim |
2009 - 2010 |
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McQ Inc Authentication for DSP-based Sensor Nodes Patrick Schaumont |
2008 - 2009 |
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McQ Inc Security Measures Applicable to DSP Architectures Patrick Schaumont |
2007 - 2008 |
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ST MicroElectornics Electronic System Level Design Patrick Schaumont |
2006 - 2007 |
Software and Artifacts
| CAPRI6: An ASIC for fault root-causing. Root-cause analysis of faults at the level of software is difficult because of the large number of abstraction levels that obfuscate the root cause of the fault effect. In particular, after a fault injection, the hardware behavior transforms from a {\em sane} machine into a {\em weird} machine, potentially changing the meaning of the software or even the instructions. The fault effect therefore becomes hard to understand, as the behavior of the hardware is no longer consistent with the original design. We developed an ASIC to help us study this problem and to define a methodology towards better root causing. The fault root causing methodology has applications in testing cryptographic protocols, fault countermeasures and potentially the hard problem of silent data corruption. |
| Saidoyoki: Evaluating Side-channel Leakage in Pre- and Post-silicon Setting. Predicting the level and exploitability of side-channel leakage from complex SoC design is a challenging task. We present Saidoyoki, a test platform that enables the assessment of side-channel leakage under two different settings. The first is pre-silicon side-channel leakage estimation in SoC, and it requires the use of fast side-channel leakage estimation from a high-level design description. The second is post-silicon side-channel leakage measurement and analysis in SoC, and it requires a hardware prototype that reflects the design description. By designing an in-house SoC and next building a side-channel leakage analysis environment around it, we are able to evaluate design-time (pre-silicon) side-channel leakage estimates as well as prototype (post-silicon) side-channel leakage measurements. The Saidoyoki platform hosts two different SoC, one based on a 32-bit RISC-V processor and a second based on a SPARC V8 processor. |
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SKIVA: Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks. We propose a customized processor called SKIVA that supports experiments with the design of countermeasures against a broad range of implementation attacks. Based on bitslice programming and recent advances in the literature, SKIVA offers a flexible and modular combination of countermeasures against power-based and timing-based side-channel leakage and fault injection. Multiple configurations of side-channel protection and fault protection enable the programmer to select the desired number of shares and the desired redundancy level for each slice. Recurring and security-sensitive operations are supported in hardware through custom instruction-set extensions. The new instructions support bitslicing, secret-share generation, redundant logic computation, and fault detection. Related Publication: P. Kiaei, D. Mercadier, P. E. Dagand, K. Heydemann, P. Schaumont, "Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks," 11th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2020), Lugano, Switzerland, April 2020. |
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FAME: Fault-attack Awareness using Microprocessor Enhancements. This website collects the key findings of the FAME project. We designed and demonstrated two chips, FAME v1 and FAME v2, which implement a microprocessor with fault-attack detection and fault-attack response capabities. |
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Masked implementations of the Advanced Encryption Standard. This github repository contains source code for masked implementations of AES, including (a) Byte-level masked AES, (b) bitsliced AES and (c) bitsliced masked AES. We release this source code under a GPL license. Related Publication: Y. Yao, M. Yang, B. Yuce, C. Patrick, P. Schaumont, "Fault-Assisted Side-Channel Analysis of Masked Implementations," IEEE HOST Symposium 2018, May 2018, Washington, DC. |
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Fault-resistant implementation of the Advanced Encryption Standard. This github repository contains source code for a bit-sliced implementation of AES, capable of handling fault detection in software. The bitsliced implementation provides intra-instruction redundancy, and is capable of handling fault attacks with high fault injection precision. Related Publication: C. Patrick, B. Yuce, N. Farhady Ghalaty, P. Schaumont, "Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy," Selected Areas in Cryptography (SAC 2016), St. John's, Canada, August 2016. |
| Bitserial
design of the SIMON Block Cipher. A compact, FPGA-oriented Verilog implementation of the SIMON Block Cipher. Related Publication: A. Aysu, E. Gulcan, P. Schaumont, "SIMON Says, Break Area Records of Block Ciphers on FPGAs," IEEE Embedded Systems Letters, 6(2):37-40, April 2014. |
A test chip for
the NIST competition of the SHA-3 standard. We designed a chip with five finalist candidates for the SHA-3 competition organized by NIST. The webpage provides Verilog source code, scripts, and publications related to the chip design and the associated SHA-3 hardware benchmarking work. Unfortunately we are no longer handing out free test samples. All gone, sorry! Related Publication: M. Srivastav, X. Guo, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates," Elsevier Microprocessors and Microsystems - Embedded Hardware Design (Special Issue on "Digital System Security and Safety"), 2012. |
| Physical Unclonable
Function Measurement Database. We have collected on-chip variability data of nearly 200 Spartan 3E FPGAs (90nm), designed functional prototypes of PUFs, analyzed aging effects, and created improved entropy extraction methods. The measurement data is available in a Github repository: ropuf_host2010. Related Publication: A. Maiti, J. Casarona, L. McHale, P. Schaumont "A Large Scale Characterization of RO-PUF," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, June 2010. |
| GEZEL Language,
Cosimulation Environment, and Code Generator. GEZEL is a cycle-based hardware description language based on the Finite-State-Machine + Datapath (FSMD) model. The GEZEL tools offer stand-alone simulation, cosimulation, and code-generation into synthesizable (VHDL) code. Through user-defined library-block extensions in C++, new cosimulation interfaces can be added. GEZEL is open-source, largely in C++. Prepackaged binaries can be installed on Ubuntu systems. Related Publication: P. Schaumont, I. Verbauwhede, "Interactive cosimulation with partial evaluation," 2004 Design Automation and Test in Europe (DATE 2004), February 2004. |