EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O IO 1 fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O fpga_0_DDR_SDRAM_DDR_Clk_pin O 1 fpga_0_DDR_SDRAM_DDR_Clk fpga_0_DDR_SDRAM_DDR_Clk_n_pin O 1 fpga_0_DDR_SDRAM_DDR_Clk_n fpga_0_DDR_SDRAM_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_DDR_Addr fpga_0_DDR_SDRAM_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_DDR_BankAddr fpga_0_DDR_SDRAM_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CAS_n fpga_0_DDR_SDRAM_DDR_CE_pin O 1 fpga_0_DDR_SDRAM_DDR_CE fpga_0_DDR_SDRAM_DDR_CS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CS_n fpga_0_DDR_SDRAM_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_RAS_n fpga_0_DDR_SDRAM_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_DDR_WE_n fpga_0_DDR_SDRAM_DDR_DM_pin O 1:0 fpga_0_DDR_SDRAM_DDR_DM fpga_0_DDR_SDRAM_DDR_DQS IO 1:0 fpga_0_DDR_SDRAM_DDR_DQS fpga_0_DDR_SDRAM_DDR_DQ IO 15:0 fpga_0_DDR_SDRAM_DDR_DQ sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET