EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_rst_pin I 1 sys_rst_s  RESET  1A fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin IO 0:1 fpga_0_DDR_SDRAM_32Mx16_DDR_DQS 2A fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin IO 0:15 fpga_0_DDR_SDRAM_32Mx16_DDR_DQ 3A fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin O 0:12 fpga_0_DDR_SDRAM_32Mx16_DDR_Addr 4A fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin O 0:1 fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr 5A fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CASn 6A fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CKE 7A fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CSn 8A fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_Clk 9A fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn 10A fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin O 0:1 fpga_0_DDR_SDRAM_32Mx16_DDR_DM 11A fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_RASn 12A fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_WEn 13B sys_clk_pin I 1 dcm_clk_s  CLK  14C fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK