ECE 4514 - Lecture 19 - QSYS Topics for final part: - Final Project - QSYS - Power Optimization - Asynchronous Logic - Clock Gating - High speed data transfer - Beyond Verilog: High level synthesis, Formal verification 5:00 Midterm 5:05 Final Project 5:10 SoC Modern complex chips are often designed as 'system-on-chip'. Take ECE 4530 for an in-depth treatment of the topic. Here, we will only look at the hardware organization aspects of SoC. An SoC typically consists of a microprocessor with one or more peripherals and/or specialized computing units. An SoC is, fundamentally, a mix-and-match between general-purpose (flexible) processing and dedicated, specialized processing. An SoC is a combination of hardware elements with a processor. The combination of hardware elements is determined by the application domain. Another way too look at it: An SoC is a mechanism to specialize a general purpose processor - data/event processing -> I/O modules: UART, IO Port -> Event Management: IRQ, timer -> Computational units: Coprocessors - storage -> RAM, ROM, Registers, .. - communication mechanisms -> Busses -> Dedicated Ports -> DMA Show examples of - MSP432 - Cyclone V FPGA-SoC - Qualcomm Snapdragon One of the key advantages of SoC is its scalability in design. The SoC follows a systematic interconnect concept. - The central controller is in charge of the overall system. The central controller maintains control over the entire system through the bus system. - Master/slave connectivity Segment 1 Segment 2 master slave master slave --------------------------------------------------- CPU MEMORY BRIDGE TIMER DMA BRIDGE UART - Bus segmentation The on-chip bus is the communication highway. It is a central shared resource. In order to improve parallelism in the system, buses are segmented - high-speed busses are separated from low speed - high-speed busses are more advanced than low speed busses - Bus Address Space The physical address space in an SoC (drawing) 5:25 Altera's SoC Altera (Intel) has defined its own SoC concept. The idea is that you can pick and place components onto a chip, and interconnect them with a bus nextwork. The standard bus interconnection network is the AVALON bus standard. AVALON defines: - component interfaces - component interconnect mechanisms When you design components with an AVALON interface, they can be flexibly placed and arranged into the SoC configuration defined for that particular FPGA chip. There are several standard interfaces defined for AVALON: AVALON-MM (memory-mapped interface) Master/Slave A bus-based interface AVALON-ST (streaming interface) Source/Sink A point-to-point interface AVALON-Conduit An 'off-chip' connection AVALON-TC Tristate Interface AVALON Reset Reset Interface AVALON Clock Clock Interface These interfaces are flexibly mixed-and-matched to build SoC systems Example: Avalon Manual Figure 1, Figure 2 5:30 Altera QSYS The tool that manages SoC interconnect in hardware, is called QSYS. QSYS is a component within Quartus. It is a block-diagram like editing tool that builds the SoC architecture, and that can generate Verilog code. The resulting Verilog code can be compiled in Quartus. +---------------------------------------------+ | FPGA | | | | +-----------------------------------+ | | | QSYS | | | | QSYS model of components | | | | with AVALON interfaces | | | +-----------------------------------+ | | | | Any Verilog | +---------------------------------------------+ The interfaces between QSYS and the General FPGA consists of: - Clock and Reset - Conduits 5:35 Example System: Setting LED and Reading Switched using system-console The following example is a QSYS system that builds a basic system-on-chip architecture with a JTAG interface. The JTAG interface is controlled by the PC connected to the FPGA. JTAG-Avalon-Master -----+------- Avalon-Slave GPIO ---> LEDs | +------- Avalon-Slave GPIO <--- Switches This system can be completely designed within QSYS DEMO. Remark the following points: - The QSYS system comes with an IP library of different (pre-made) components (left pane) - Each module has several different interfaces. In this case each interface is one of the following: - clock - reset - master - slave - conduit - The system has a memory map per Avalon Master. In this case: LED.s1 0x0000_0010 - 0x0000_001f SWITCH.s1 0x0000_0000 - 0x0000_000f This means that an Master write on the avalon bus to address 0x10 will be received by the LED (relative address 0). A master read from the avalon bus on address 0x0 will be taken from the SWITCH (relative address 0) - Both LED and SWITCH are GPIO and have several control registers: 0x0 GPIO Data read/write 0x4 GPIO Direction 0x8 GPIO Interrupt Mask 0xC GPIO Edge Capture - The FPGA_level I/O for this QSYS system is defined therough the 'export' signals, which collect (essentially) clock, reset, and conduits. - After generating HDL, you then need to compile the bitstream and configure the FGPA - System-level interconnect: ---------------------------------------------------------------- module platformdemo( input CLOCK_50, input [3:0] KEY, output [9:0] LEDR, input [9:0] SW ); wire [7:0] led, switch; wire reset; qsystop u0 ( .clk_clk (CLOCK_50), .reset_reset_n (reset), .ledout_export (led), .switchin_export (switch) ); assign LEDR[7:0] = led; assign switch = SW[7:0]; assign reset = KEY[0]; // quartus_sh --flow compile platformdemo // quartus_pgm -m jtag -o "p;platformdemo.sof@2" endmodule ---------------------------------------------------------------- 5:45 SYSTEM-CONSOLE The system we just build can be controlled from a PC through an application called system-console. This application uses the JTAG interface to connect to the jtag avalon-master. From there, we can control the modules of the QSYS system. system-console itself is a scripting interface that supports several different 'services'. One of these services is to be an AVALON master. The following script is a system-console example that will control the LEDs and read the switches. -------------------------------------------------------------- set jtag_master [lindex [get_service_paths master] 0] open_service master $jtag_master for {set i 0} {$i<256} {incr i} { # read switches set m [master_read_8 $jtag_master 0x0 1] # copy to LED master_write_8 $jtag_master 0x10 $m # wait 100ms after 100 } -------------------------------------------------------------- DEMO 5:55 Building custom QSYS components We can now add our own custom QSYS components. They can be integrated as long as they have an AVALON interface (MM, ST, Conduit, ..). The AVALON Interface specifications describe the precise signal names to be used for each connection. For example, for an Avalon Slave: address - (relative) slave byte address read - read control signal (master is reading) readdata - data going back to master (typically 32 bit) write - write control signal (master is writing into slave) writedata - data coming from master (typically 32 bit) ... and many others - cfr AVALON Interface Definition Document Here is an example of a component that drives the HEX displays. slave byte address 0: HEX value to display slave byte address 4: if (1), increment value approx 2 times per second if (0), hold the value ---------------------------------------------------------------- module hexdriver( input wire clk, input wire reset, input wire address, input wire write, input wire [31:0] writedata, output wire [6:0] HEX0, output wire [6:0] HEX1, output wire [6:0] HEX2, output wire [6:0] HEX3, output wire [6:0] HEX4, output wire [6:0] HEX5 ); reg [23:0] hexval, hexvalnext; reg mode, modenext; reg [23:0] cnt, cntnext; seg7decoder H0(hexval[ 3: 0], HEX0); seg7decoder H1(hexval[ 7: 4], HEX1); seg7decoder H2(hexval[11: 8], HEX2); seg7decoder H3(hexval[15:12], HEX3); seg7decoder H4(hexval[19:16], HEX4); seg7decoder H5(hexval[23:20], HEX5); always @(posedge clk) if (reset == 1'h1) begin cnt <= 24'h0; hexval <= 24'h0; mode <= 1'h0; end else begin cnt <= cntnext; hexval <= hexvalnext; mode <= modenext; end wire write_hexval; wire write_mode; assign write_hexval = (write & (address == 1'h0)); assign write_mode = (write & (address == 1'h1)); always @(*) begin hexvalnext = hexval; modenext = mode; cntnext = cnt + 24'h1; if (write_mode) modenext = writedata[0]; if (write_hexval) hexvalnext = writedata[23:0]; else if (mode & (cnt == 24'h0)) hexvalnext = hexval + 24'h1; end endmodule ---------------------------------------------------------------- Making use of hexdriver requires an extra integration step. First, the component needs to be added to QSYS. DEMO Then, the component can be integrated into the QSYS system DEMO -> Load platformdemo2 application and compile it into a bitstream Finally, here is an example script that demonstrates the use of the new hexdriver component. ---------------------------------------------------------------- set jtag_master [lindex [get_service_paths master] 0] open_service master $jtag_master # write 0xADECAF into hex displays master_write_32 $jtag_master 0x20 0xADECAF # enable counting master_write_32 $jtag_master 0x24 0x1 # wait 10 seconds after 10000 # disable counting master_write_32 $jtag_master 0x24 0x0 # read switches and copy to hex displays set m [master_read_8 $jtag_master 0x0 1] master_write_32 $jtag_master 0x20 $m ---------------------------------------------------------------- This can also be run as a system-console application 6:05 Summary - QSYS is a block-level based design tool that significantly accelerates hardware design - It does this be restricting the hardware interfaces between modules to a few standardized interfaces. Typically, memory-mapped and streaming (point to point) interfaces - While QSYS is typically used in the context of system on chip (with a central processor), it can also be used for hardware design and hardware debug.