Lecture 12: Signaltap

- Summary recap on FPGA technology
- Signaltap principle
- Homework 5 demo
- Homework 5 solution strategy

5:00 FPGA Technology
(This is what we did not discuss on Tue)

The basic concept of programmable gate array logic is the provide
a chip to the customer that can be customized in the field (hence
the name). Programming involves two aspects:

   - Deciding on the logic function that needs to be implemented
   - Storing the configuration that determines the logic function

There are commonly three different strategies to store the programming
of an FPGA:

   1. Fuse based FPGA: 

      The programming is done once by blowing fuses, or by 
      connecting them (antifuses).

      This is a program-once technology. The advantage is that 
      fuses are small, and that the configuration can be stored
      on-chip. The disadvantage, of course, is that the functionality
      cannot be changed.

   2. Nonvolatile (flash-based) FPGA:

      The configuration is stored in EEPROM cells, nonvolatile memory
      cells that are located on chip. EEPROM requires extra processing
      steps, making the manufacturing of such FPGA more expensive.

   3. Volatile (SRAM-based) FPGA:

      The configuration is stored in SRAM cells, located on the chip.
      This is the most popular technology at the moment, and both market
      leaders (Xilinx and Intel, formerly Altera) concentrate on
      SRAM-based FPGA. The disadvantage is that the configuration content
      needs to be stored off-chip, and before the chip can be used,
      you have to configure it. 

The early generations of FPGA were called Programmable Logic Arrays.
These chips where specialized in implementing logic functions.

(slide 6, 7)

More recent generations of FPGA's use a regular array of logic
functions, interleaved with a regular array of interconnect.

A modern FPGA uses an 'island style' arrangement.
There are five configurable elements in such an FPGA:
  1/ There are logic elements, called Configurable Logic BLock (Xilinx)
     are Logic Elements (Altera)
  2/ There are memory elements, hard macros of memory cells
  3/ There are configurable multipliers, hard macros with arithmetic logic
  4/ There are dedicated clock generation and distribution elements
  5/ There are configurable input/ouput pins
 
5:10 Logic elements in the Cyclone V

(slide 10-11)

The logic elements:
   - contain lookup tables
   - contain registers
   - contain carry chains

Each logic element can thus serve for different purposes:
   - flip-flop storage
   - lookup table logic function
   - both storage and lookup table logic function

The logical elements are arranged in blocks of 10, called LAB
or MLAB. These blocks connect to local interconnect and global row/
column interconnect.

The idea is that there is a hierarchy on the network. Short connections
between logic elements can be done through small, short wires (ie deepest
layer metal). Long connections between LE's far apart will need to take the
'highway' of global interconnect, which can carry a limited set of signals
across the chip, very quickly.

5:15 Memory elements in the Cyclone V

(slide 12)

Besides these logic elements, the Cyclone V can implement
memory modules - RAM modules that accept an address. We will
discuss the instantiation of these later.

The Cyclone V A5 has:
	446 blocks of 'M10K' modules, configurable 10 kilobit RAM modules
	679 blocks of MLAB modules, configurable 640 bit modules built from logic elements

	In total, the Cyclone V A5 chip has 4,884 Kilobit of on-chip memoru.

5:20 DSP elements in Cyclone V

(slide 13)

Multipliers are extensively used in signal processing, communications, accelerated scientific computation. FPGA have dedicated multipliers on board. Why? Because they are much faster then the multipliers you would implement using configurable logic elements.

The DSP elements contain multiply-accumulation logic.

The Cyclone V A5 has:
    150 DSP modules.
    This means it can do up to 300 18*18 bit multiplies PER CLOCK CYCLE.

5:30 Signaltap

(diagram)

   signal    ---> On-chip Buffer ---------------> PC timing diagram
   clock   -----> Sample rate for buffer
   trigger   ---> Start condition for sample

Design Flow for signaltap

   1. Configure Signaltap Logic Analyzer
   2. Define Triggers
   3. Compile Design
   4. Program Target
   5. Enable Trigger
   6. View and Analyze Data

Demonstration on Tonegen

Demo 1: I2C protocol
        Decode the I2C device address send to the device
        - trigger: I2C clock down and I2C data high
        - clock frequency: 50MHz / 2^7 ~ 390 KHz

Demo 2: Audio Interface to Codec
        Decode the BCLK/LRCK signalling
        - trigger: upedge on firstsample
        - clock frequency: 50MHz 

5:50 Homework 5 tips

- Explain operation of audiogen
- Explain integration with sine wave generation

6:00 Happy Spring Break