Lecture 31: Synchronous Interface: SPI -------------------------------------- 10:10 Clock Synchronization and Arbitration in I2C * So far, we have studied I2C systems with a single master (and multiple slaves). * We have worked with the following I2C transfers - Single Byte Write - Single Byte Read - Multi Byte Write - Multi Byte Read * We have studied how I2C is applied in the context of typical chip interfaces (Thermal Sensor, Light Sensor). Notice that such an interface is a logical hierarchy: MSP432 Sensor "Read Temperature" Temp Sensing HW | | Read 16 bit from Register T Store in reg T | Read/Write reg operation Multi-byte I2C read | slave address of sensor I2C interface | | Electrical Connectivity Electrical Connectivity +-----------------------------------+ * You may have noticed that BOTH SDA and SCL are tri-state ports They can both be input as well as output. The default operation is like this: Master Slave ----------------------------------------------------------------------- SCL Writes Clock Pulses Listens to Clock Pulses ----------------------------------------------------------------------- SDA Writes for Master->Slave Reads for Master->Slave data xfer Reads for Slave->Master Writes for Slave->Master data xfer ----------------------------------------------------------------------- * So the question comes: under what conditions would SCL work as an input? It turns out there are two different occasions: for synchronization, and for arbitration. We will discuss each next. 10:15 Clock Synchronization (See UM10204 3.1.7) In multi-master systems, all masters must run at the same speed, since all of them can generate a clock. They apply the following technique to generate a common system clock. - Each master has defined a CLOCK-HIGH and a CLOCK-LOW period. That period does not have to be the same for each master. The synchronization algorithm still guarantees that all masters will use a common clock. The clock is defined by the LONGEST CLOCK-LOW and the SHORTEST CLOCK-HIGH period in the system, and the synchronization works as follows: - Each master samples the clock line (SCL) continuously. When the SCL goes low, while the master has not driven a low onto the line, it concludes another master must be initiating the low phase. In response, the master will also drive a low on SCL. It will start an internal counter that counts off the CLOCK-LOW period. - When the internal counter expires at CLOCK-LOW, the master will release the SCL line to high. Again, the SCL is sampled and checked if it is high. If not, the master concludes there is another master in the system who is still counting through CLOCK-LOW. The master therefore goes in a wait status, waiting for SCL to go high. - When SCL is finally high, all master will start counting the CLOCK-HIGH period. All master do this at the same time, since they were either waiting for SCL to go high, or else have just reach the start of CLOCK-HIGH. - All masters now count off the CLOCK-HIGH period. The first one who expires, will pull SCL low again, which restarts the synchronization. 10:20 Arbitration (See UM10204 3.1.8) Even cooler is that the masters in a multi-master system can find out if they are in competition with each other (ie. try to drive the bus at the same time). The algorithm works as follows. During every bit, when SCL is high, each master will check of the SDA value on the line matches the value it wants to drive. This should always match, except for the following situation: a master wants to drive a logic-high, while another master wants to drive a logic-low (collision). The value of SDA will be LOW, because of the open-collector design of I2C. The master who detects this collision (ie. sensing 0 while writing 1) will loose arbitration - it has to turn off its SDA driver and abort the transfer until it sees a STOP condition. Note that this arbitration algorithm is defined solely by the data communicated over the bus. There is no fixed priority between masters, and there is no dedicated hardware that handles the arbitration. 10:30 SPI Communications SPI stands for Serial Peripheral Interconnect - It was introduced by Motorola in the 80's - Still very important today Eg. SD cards Flash Memory on Board LCD Displays (eg display on BoostXL) - Master/slave bus with a single slave and full-duplex communication - Four wires: SCK Serial Clock (TI calls it CLK) MOSI Master Out Slave In (TI calls is SIMO) MISO Master In Slave Out (TI calls it SOMI) SS Slave Select (TI calls it STE) SPI point to point Master Slave +-------------+ +-------------+ | SIMO +------->--------+ SIMO | data master to slave | SOMI +-------<--------+ SOMI | data slave to master | | | | | CLK +------->--------+ CLK | clock +-------------+ +-------------+ SPI bus Master Slave +-------------+ +-------------+ | SIMO +------->--------+ SIMO | data master to slave | SOMI +-------<--------+ SOMI | data slave to master | | | | | CLK +------->--------+ CLK | clock | STE +------->--------+ STE | slave select (each slave) | STE2 +--.. | | +-------------+ +-------------+ Comparison between I2C, SPI SPI I2C ------------------------ Max bitrate 20 Mbit/s 1 Mbit/s ------------------------ Pins 3 + n. SS 2 ------------------------ Max # Slaves n 128 ------------------------ Typical application PCB PCB ------------------------ Pros Simple Few pins High Speed Multimaster ------------------------ Cons Short Slowest ------------------------ 10:35 SPI communications in further detail Let's assume a point to point case, and draw the interconnection hardware between two SPI interfaces, a master and a slave Master Slave SIMO SIMO +->SPI Shift Reg -->----+-------+->--SPI Shift Reg------------+ | | | SOMI SOMI | +-----------------------+-------+--<--------------------------+ There are two shift registers, one in the master and one in the slave. When the master transmits a byte, it will simultaneously receive a byte from the slave. In other words, a byte 'transmission' in SPI actually means swapping two bytes between the master and the slave. When the master has noting to send, it will put a dummy byte in the shift register. When the slave has noting the send, it will put a dummy byte in the shift register. In each SPI peripheral, there are two buffers besides the shift register. - The transmission buffer TXBUF, which holds the next byte to be transmitted. - The receive buffer RXBUF, which holds the last byte received. MASTER | SLAVE | SOMI | SOMI +-------------------------<----|-----------------------------------+ | | | | TXBUF | TXBUF | | | | | | | V SIMO | SIMO V | +->RXSHIFT TXSHIFT ----->--|--------- RXSHIFT TXSHIFT ---+ | | | V | V RXBUF | RXBUF | 10:45 Clock Phase and Clock Polarity When a data byte is shifted out, the clock signal will indicate when each new bit is ready. The 'clock polarity' indicates the valid edge of the clock. CKPL = 0 indicates active clock edge is upgoing CKPL = 1 indicates active clock edge is downgoing The 'clock phase' indicates when the output is asserted relative to the input being captured. CKPH = 0 means the output is asserted on the active clock edge CKPH = 1 means the input is captured on the active clock edge So if we combine both concepts we get the following CKPL CKPH Meaning 0 0 Data is output on the rising edge of CLK. Input data is latched on the falling edge. 0 1 Data is output one half-cycle before the first rising edge of CLK and on subsequent falling edges. Input data is latched on the rising edge of CLK. 1 0 Data is output on the falling edge of CLK. Input data is latched on the rising edge. 1 1 Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of CLK. Example 1 - CKPL = 0 and CKPH = 0 * * * +-----+ +-----+ +-----+ CLK | | | | | | +-----+ +-----+ +-----+ +-----+ +----- ----------- ----------- ----------- --- SOMI X b7 X b6 X b5 X +----- ----------- ----------- ----------- --- | | | +----- ----------- ----------- --------- SIMO X b7 X b6 X b5 +----- ----------- ----------- --------- Example 2 - CKPL = 0 and CKPH = 1 * * * +----+ +-----+ +-----+ +-----+ CLK | | | | | | | +-----+ +-----+ +-----+ +-----+ +----- ----------- ----------- ----------- --- SOMI X b7 X b6 X b5 X +----- ----------- ----------- ----------- --- | | | +----- ----------- ----------- --------- SIMO X b7 X b6 X b5 +----- ----------- ----------- --------- Example 3 - CKPL = 1 and CKPH = 0 * * * * +-----+ +-----+ +-----+ +-----+ CLK | | | | | | | | + +-----+ +-----+ +-----+ +---- +----- ----------- ----------- ----------- --- SOMI X b7 X b6 X b5 X +----- ----------- ----------- ----------- --- | | | +----- ----------- ----------- --------- SIMO X b7 X b6 X b5 +----- ----------- ----------- --------- Example 4 - CKPL = 1 and CKPH = 1 * * * +-----+ +-----+ +-----+ CLK | | | | | | +-----+ +-----+ +-----+ +---- +----- ----------- ----------- ----------- --- SOMI X b7 X b6 X b5 X +----- ----------- ----------- ----------- --- | | | +----- ----------- ----------- --------- SIMO X b7 X b6 X b5 +----- ----------- ----------- --------- 10:50 SPI Peripherals in the MSP432 There are four eUSCI_A modules and four eUSCI_B modules. Both of them support SPI. So, there are up to 8 SPI ports on the MSP432 (100-pin PZ package) However, the total sum of UART ports, I2C ports, and SPI ports cannot be larger than 8. The eUSCI_A peripheral can work as UART or SPI. The eUSCI_B peripheral can work as I2C or SPI. Cfr block diagram of the SPI peripheral 10:58 Summary - Synchronous Peripheral Interface Point to point, uses four signals (clk, select, data-in, data-out) Master/Slave concept - Programming: For every byte send, must receive one byte The application can decide what to do with these bytes - Wednesday - online programming example on the Cerebot board (will be posted as a recorded video) - Friday - Quiz Friday - Lab 3 due data - Will hold online office hours (chat) at a time to be announced