ECE 2534 Lecture 28: The I2C Bus

10:10 Asynchronous and Synchronous Serial Interfaces

So far, we discusssed the UART as device to support serial data transmission. 
The UART is asynchronous, and needs only two wires (RX and TX) in addition to 
ground to enable communication.

The two interfaces we will discuss in the coming lectures, are synchronous. 
The two interfaces we will discussed are called SPI and I2C:
	I2C = Inter Integrated Circuit
	SPI = Synchronous Peripheral Interface

We will put the emphasis on I2C (today, tomorrow, Monday).
	
A synchronous interface contains a clock signal besides the data signal.
The clock signal synchronizes the transmission between the sender and receiver. 
The device that generates the clock signal is called the
MASTER, while the device that is synchronized by the clock signal is 
called the SLAVE.

The clock signal for I2C and SPI should not be confused with the
system clock of the microcontroller (SYSCLK). The clock signal
of I2C and SPI is a logical clock, a data signal that is driven
high and low by the master to transmit synchronizing edges.

10:15 Interconnect mechanisms

I2C
        Master                           Slave
	+-------------+      bidir     +-------------+
	|         SDA +---<-------->---+ SDA         | data 
	|             |                |             |
	|         SCL +------->--------+ SCL         | clock
	+-------------+                +-------------+

I2C with multiple slaves

        Master                           Slave
	+-------------+                +-------------+
	|         SDA +---<-----+-->---+ SDA         | data 
	|             |         |      |             |
	|         SCL +-----+->-|------+ SCL         | clock
	+-------------+     |   |      +-------------+
                        |   |
	                    |   |                Slave
	                    |   |      +-------------+
	                    |   +-->---+ SDA         | data 
	                    |          |             |
	                    +->--------+ SCL         | clock
	                               +-------------+

SPI point to point

        Master                           Slave
	+-------------+                +-------------+
	|         SDO +------->--------+ SDI         | data master to slave
    |         SDI +-------<--------+ SDO         | data slave to master
	|             |                |             |
	|         SCK +------->--------+ SCK         | clock
	+-------------+                +-------------+

SPI bus

        Master                           Slave
	+-------------+                +-------------+
	|         SDO +------->--------+ SDI         | data master to slave
    |         SDI +-------<--------+ SDO         | data slave to master
	|             |                |             |
	|         SCL +------->--------+ SCL         | clock
	|          SS +------->--------+ SS          | slave select (each slave)
    |         SS2 +--..            |             | 
	+-------------+                +-------------+
	
UART

	+-------------+                +-------------+
	|          TX +------->--------+ RX          | data reception
	|             |                |             |
	|          RX +-------<--------+ TX          | data transmission
	+-------------+                +-------------+

10:25 Comparison between UART, I2C, SPI
	
					SPI			I2C			UART
                    ----------------------------------------
Max bitrate			20 Mbit/s	1 Mbit/s	500 Kbit/s
                    ----------------------------------------
Pins				3 + n. SS	2			2
                    ----------------------------------------
Max # Slaves		n			128			(point to point)
                    ----------------------------------------
Typical application	PCB         PCB			Terminals
                    ----------------------------------------
Pros				Simple		Few pins	Long Distance
					High Speed	Multimaster
                    ----------------------------------------	
Cons				Short		Slowest		Asynchronous
                    ----------------------------------------	


I2C was developed by Philips (now NXP) in the 80's. Currently the I2C 
standard is supported by many manufacturers including TI, Siemens, ST, 
NEC, Freescale and Microchip. I2C has several versions (and generations):

		Original (original, 1982)	100 kbps
		Standard v1 (1992)			400 kbps  -> still prevailing
		Current v6 (2016)			5 Mbps

10:35 Electrical Design

	SCL -------------+---------------------+----------/// pullup ///--- Vdd
	                 |                     |
	SDA --------+----|-----------------+---|----------/// pullup ///--- Vdd
	            |    |                 |   |
				|    |                 |   |
			   SDAm  SCLm             SDAs SCLs
			   
			    Master                 Slave
				open collector		   open collector
			     
				 
Each master and each slave has a bidirectional I/O port using
a tri-state output.

The maximum capacitive load allowed on the bus is 400pF.
This limits the bus length and the number of slaves.
There is also a logical limit for the number of slaves
determined by the number of available slave addresses
(128 for the original bus, 1008 for the 1992 version of the bus)

10:40 The I2C transfer Protocol

Refer to slides:
	- Transmitting a bit
	- Start and Stop
	- Byte Format
	- Complete I2C transfer
  
- Protocol for single-byte data write

     Master |  Start | Address+W |     | BYTE |     | STOP
     -------|--------|-----------|-----|------|-----|------
     Slave	|        |           | ACK |      | ACK |

- Protocol for single-byte data read

     Master |  Start | Address+R  |     |     | NACK | STOP
     -------|--------|------------|-----|-----|------|-----
     Slave	|        |            | ACK | BYTE|      | 

- Protocol for multi-byte data write

     Master |  Start | Address+W |     | BYTE |     |BYTE |    |STOP
     -------|--------|-----------|-----|------|-----|-----|----|-----
     Slave	|        |           | ACK |      | ACK |     |ACK |

- Protocol for multi-byte data read

     Master |  Start | Address+R |     |      | ACK |      | NACK | STOP
     -------|--------|-----------|-----|------|-----|------|------|------
     Slave	|        |           | ACK | BYTE |     | BYTE |      | 

10:50 Assignment: Decode the transfers shown on slide 9 & 10

10:80 Summary