Publications

Articles

2024

M. S. Safa, P. Schaumont and S. Tajik, "Parasitic Circus: On the feasibility of golden-free PCB Verification," Design Automation and Test in Europe (DATE 2024), Valencia, Spain, March 2024.
doi Y. Yao, P. Kiaei, R. Singh, S. Tajik and P. Schaumont "Programmable RO (PRO): A Multipurpose Countermeasure Against Side-Channel and Fault Injection Attack," in J. Szefer, R. Tessier (eds) Security of FPGA-Accelerated Cloud Computing Environments. Springer 2024.

2023

doi J. Feldtkeller, T. Gueneysu, P. Schaumont, "Quantitative Fault Injection Analysis," Asiacrypt, December 2023.
doi P. Schaumont "Lightning Talk: The Incredible Shrinking Black Box Model," Design Automation Conference (DAC), July 2023.
pdf Z. Liu, P. Schaumont, "Root-cause Analysis of the Side Channel Leakage from ASCON implementations," NIST Lightweight Cryptography Workshop 2023, June 2023.
pdf P. Schaumont, "You Can Hide But You Can't Verify: On Side-channel Countermeasure Verification," Workshop on SSH-SoC: Safety and Security in Heterogeneous Open System-on-Chip Platforms, July 2023. Best Paper Award.
doi P. Kiaei, Y. Yao, Z. Liu, N. Fern, C.-B. Breunesse, J. Van Woudenberg, K. Gillis, A. Dich, P. Grossmann, P. Schaumont, "Gate-Level Side-Channel Leakage Ranking with Architecture Correlation Analysis," IEEE Transactions on Emerging Topics in Computing, April 2023.
doi D. Shanmugam, P. Schaumont, "Improving Side-channel Leakage Assessment using Pre-silicon Leakage Models," 14th International Workshop on Constructive Side-channel Analysis and Secure Design (COSADE 2023), Munch, Germany, April 2023.
doi R. Singh, S. Islam, B. Sunar, P. Schaumont, "Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium," ACM Transcations on Embedded Computing Systems (TECS), March 2023.
doi T. Mosavirik, P. Schaumont, S. Tajik, "ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection," IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(1), 301–325.

2022

doi P. Kiaei. T. Conroy, P. Schaumont, "Architecture Support for Bitslicing," in IEEE Transactions on Emerging Topics in Computing, 2022. Also as IACR ePrint 2021/1236, 2021.
doi artifact P. Kiaei, P. Schaumont, "SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs," IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022(4), 751–773.
doi S. Tajik, P. Schaumont, "The Technological Arms Race in Hardware Security," 2022 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, Special Session on Hardware Security for a Smart Society, August 2022.
preprint P. Kiaei, Y. Yao, Z. Liu, N. Fern, C.-B. Breunesse, J. Van Woudenberg, K. Gillis, A. Dich, P. Grossmann, P. Schaumont, "Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis," arXiv:2204.11972, April 2022.
doi P. Schaumont, "Emerging Computing Challenges in the Interaction of Hardware and Software," IEEE Computer 55(9): 4-5 (2022).
preprint R. Singh, S. Islam, B. Sunar, P. Schaumont, "An End-to-End Analysis of EMFI on Bit-sliced Post-Quantum Implementations," arXiv:2204.06153, April 2022.
preprint doi P. Kiaei, Z. Liu, P. Schaumont, "Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment," Great Lakes Symposium on VLSI, June 2022.
preprint S. Islam, K. Mus, R. Singh, P. Schaumont, B. Sunar, "Signature Correction Attack on Dilithium Signature Scheme," Euro S&P, June 2022.
doi I. Buhan, L. Batina, Y. Yarom, P. Schaumont, "SoK: Design Tools for Side-Channel-Aware Implementions," AsiaCCS, June 2022.
link Z. Liu, P. Schaumont, "Root-cause Analysis of Power-based Side-channel Leakage in Lightweight Cryptography Candidates," NIST 5th Lightweight Cryptography Workshop, May 2022.
doi A. S. Krishnan, P. Schaumont, "Benchmarking And Configuring Security Levels In Intermittent Computing," ACM Transactions on Embedded Computing Systems, February 2022.
doi T. Mosavirik, F. Ganji, P. Schaumont, S. Tajik, "ScatterVerif: Verification of Electronic Boards Using Reflection Response of Power Distribution Network," ACM J Emerging Technologies in Computing Systems, 2022, preprint.
doi V. Vakhter, B. Soysal, P. Schaumont, U. Guler, "Threat Modeling and Risk Analysis for Miniaturized Wireless Biomedical Devices," IEEE Internet of Things Journal, 2022, preprint.

2021

pdf I. Buhan, L. Batina, Y. Yarom, P. Schaumont, "SoK: Design Tools for Side-Channel-Aware Implementions," arXiv:2104.08593v1, 2021.
doi J. Grycel, P. Schaumont, "SimpliFI: Hardware Simulation of Embedded Software Fault Attacks" Cryptography 2021, 5, 15.
doi P. Kiaei, P. Schaumont, "Synthesis of Parallel Synchronous Software" IEEE Embedded Systems Letters, 13(1), 2021.
preprint P. Kiaei, C-B Breunesse, M. Ahmadi, P. Schaumont, J. Van Woudenberg, "Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection," Design Automation Conference 2021, December 2021.
preprint P. Kiaei, Z. Liu, R. K. Eren, Y. Yao, P. Schaumont, "Saidoyoki: Evaluating Side-channel Leakage in Pre- and Post-silicon Setting," IEEE SOCC 2021, September 2021. Preprint IACR ePrint Archive: Report 2021/1235.
doi P. Schaumont, "Socially-Distant Hands-On Labs for a Real-time Digital Signal Processing Course," Great Lakes Symposium on VLSI 2021, June 2021.
pdf Y. Yao, P. Kiaei. R. Singh, S. Tajik, P. Schaumont, "Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attack," arXiv:2106.13784, 2021.
pdf Y. Yao, T. Tufan, T. Kathuria, B. Ege, U. Guler, P. Schaumont, "Pre-silicon Architecture Correlation Analysis (PACA): Identifying and Mitigating the Source of Side-channel Leakage at Gate-level," IACR ePrint Archive: Report 2021/530, 2021.

2020

doi A. S. Krishnan, C. Suslowicz, P. Schaumont, "Secure and Stateful Power Transitions in Embedded Systems" Journal of Hardware and System Security, Special Issue on SPACE 2018, 4, 263-276, 2020.
pdf P. Kiaei, A. S. Krishnan, P. Schaumont, "Parallel Synchronous Code Generation for Second Round Light Weight Candidates," 4th Lightweight Cryptography Workshop, NIST, October 2020.
doi R. Singh, T. Conroy, P. Schaumont, "Variable Precision Multiplication for Software-Based Neural Networks," 2020 IEEE High Performance Extreme Computing Conference, September 2020.
doi Y. Yao, P. Schaumont, J. van Woudenberg, C.B. Breunesse, E. M. Santillan, S. Stecyk, "Verification of Power-based Side-channel Leakage through Simulation," 63rd IEEE International Midwest Symposium on Circuits and Systems, August 2020.
doi V. Vakhter, B. Soysal, P. Schaumont, and U. Guler, "Minimum On-the-node Data Security for the Next-generation Miniaturized Wireless Biomedical Devices," 63rd IEEE International Midwest Symposium on Circuits and Systems, August 2020.
preprint P. Kiaei, P. Schaumont, "Domain-Oriented Masked Instruction Set Architecture for RISC-V," Workshop on Secure RISC-V Architecture Design (SECRISCV), August 2020. Also as IACR ePrint archive 2020/465 (preprint).
preprint A. Krishnan, Y. Yang, P. Schaumont, "Risk and Architecture factors in Digital Exposure Notification," International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XX), July 2020. Also IACR ePrint archive 2020/582 (preprint).
preprint Y. Yao, T. Kathuria, B.Ege, and P. Schaumont, "Architecture Correlation Analysis: Identifying the Source of Side-channel Leakage at Gate-level," IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2020), May 2020, San Jose, CA.
preprint Y. Yao, E. De Mulder, A. Kochepasov, P. Schaumont and M. Tunstall "Augmenting Leakage Detection using Bootstrapping," 11th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2020), Lugano, Switzerland, April 2020.
preprint P. Kiaei, D. Mercadier, P. E. Dagand, K. Heydemann, P. Schaumont, "Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks," 11th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2020), Lugano, Switzerland, April 2020. IACR ePrint architve 2020/466.
doi J. Knechtel, E. B. Kavun, F. Regazzoni, A. Heuser, A. Chattopadhyay, D. Mukhopadhyay, D. Soumyajit, Y. Fei, Y. Belenky, I. Levi, T. Güneysu, P. Schaumont and I. Polian, "Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA," Design Automation and Test in Europe (DATE 2020), Grenoble, FR, March 2020.
doi R. Canetti, M.van Dijk, H. Maleki, U. Rührmair and P. Schaumont, "Using Universal Composition to Design and Analyze Secure Complex Hardware Systems," Design Automation and Test in Europe (DATE 2020), Grenoble, FR, March 2020.
pdf X. Cheng, H. Yang, A. S Krishnan, P. Schaumont, Y. Yang, "KHOVID: Interoperable Privacy Preserving Digital Contact Tracing," arXiv:2012.09375v1, 2020.

2019

doi B. Yuce, C. Deshpande, M. Ghodrati, A. Bendre, L. Nazhandali, P. Schaumont, "A Secure Exception Mode for Fault-Attack-Resistant Processing" IEEE Transactions on Dependable and Secure Computing, 16(3):388-401, 2019.
preprint P. Kiaei, D. Mercadier, P. E. Dagand, K. Heydemann, P. Schaumont, "SKIVA: Flexible and Modular Side-channel and Fault Countermeasures," IACR ePrint 2019/756.
pdf A. Krishnan, P. Schaumont "Hardware Support for Secure Intermittent Architectures (Extended Abstract)," Workshop on Energy-Secure System Architectures (ESSA), May 2019.
preprint D. Dinu, A. Krishnan, P. Schaumont "SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2019.
doi A. Krishnan, C. Suslowicz, D. Dinu, P. Schaumont "Secure Intermittent Computing Protocol: Protecting State Across Power Loss," Design Automation and Test in Europe (DATE 2019), Florence, IT, March 2019.
pdf G. Venkataramani, P. Schaumont, D. Kaeli, M. Prvulovic, S. Devadas, D. Ponomarev, G. Qu, Y. Fei, "Workshop Report on NSF Workshop on Side and Covert Channels in Computing Systems," February 2019.

Before 2019

doi B. Yuce, P. Schaumont, M. Witteman "Fault Attacks on Secure Embedded Software: Threats, Design, Evaluation" Springer Journal of Hardware and Systems Security, May 2018.
doi E. De Mulder, T. Eisenbarth, P. Schaumont, "Identifying and Eliminating Side-channel Leaks in Programmable Systems" IEEE Design and Test, 35(1):74-89, February 2018.
doi A. Krishnan, P. Schaumont, "Exploiting Security Vulnerabilities in Intermittent Computing," 8th International Conference on Security, Privacy and Applied Cryptography Engineering (SPACE 2018), Kanpur, India, 2018.
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C. Suslowicz, A. Krishnan, D. Dinu, P. Schaumont, "Secure Application Continuity in Intermittent Systems," 9th International Green and Sustainable Computing Conference (IGSC18), Pittsburgh, PA, 2018.
doi Y. Yao, P. Schaumont, "A Low-cost Function Call Protection Mechanism Against Instruction Skip Fault Attacks," 2018 Workshop on Attacks and Solutions in Hardware Security (ASHES), Toronto, Canada, October 2018.
doi M. Wu, S. Guo, P. Schaumont, C. Wang, "Eliminating Timing Side-channel Leaks Using Program Repair," International Symposium on Software Testing and Analysis (ISSTA 2018), July 2018.
doi Y. Yao, M. Yang, B. Yuce, C. Patrick, P. Schaumont, "Fault-Assisted Side-Channel Analysis of Masked Implementations," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2018.
doi M. Ghodrati, S. Gujar, B. Yuce, P. Schaumont, L. Nazhandali, "Inducing Local Timing Fault through EM Injection," Proc. Design Automation Conference (DAC18), San Francisco, CA, June 2018.
doi B. Yuce, N. F. Ghalaty, C. Deshpande, H. Santapuri, C. Patrick, L. Nazhandali, P. Schaumont "Analyzing the Fault Injection Sensitivity of Embedded Software" ACM Transactions on Embedded Computing Systems, 16(4), article 95, September 2017.
doi H. Rawat, P. Schaumont, "Vector Instruction Set Extensions for Efficient Computation of KECCAK" IEEE Transactions on Computers, 66(10):1778-1789, May 2017.
doi C. Wang, P. Schaumont, "Security by compilation: an automated approach to comprehensive side-channel resistance" ACM SIGLOG News 4(2):76-89, April 2017.
doi C. Suslowicz, A. Krishnan, P. Schaumont, "Optimizing Cryptography in Energy Harvesting Applications," 2017 Workshop on Attacks and Solutions in Hardware Security (ASHES), Dallas, TX, November 2017.
doi C. Deshpande, B. Yuce, P. Schaumont and L. Nazhandali, "Employing Dual-complementary Flip-Flops to Detect EMFI Attacks," 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Beijing, CN, October 2017.
doi M. Taha, A. Reyhani-Masoleh, P. Schaumont, "Stateless Leakage Resiliency from NLFSRs," IEEE Symposium on Hardware Oriented Security and Trust (HOST 2017), McLean, VA, May 2-17.
doi A. Aysu, Y. Wang, P. Schaumont, M. Orshansky, "A New Maskless Debiasing Method for Lightweight Physical Unclonable Functions," IEEE Symposium on Hardware Oriented Security and Trust (HOST 2017), McLean, VA, May 2-17.
doi N.F. Galathy, B. Yuce, P. Schaumont. "A Systematic Approach to Fault Attack Resistant Design," in S. Bhunia, S. Ray, S. Sur-Kolay Eds., "Fundamentals of IP and SoC Security," Springer, 2017.
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P. Schaumont, "Security in the Internet of Things: A Challenge of Scale," Design Automation and Test in Europe (DATE 2017), Lausanne, CH, March 2017.
C. Wang, P. Schaumont, "Security by Compilation: An Automated Approach to Side-channel Resistance," ACM SIGLOG News, 4(2), April 2017.
doi A. Aysu, P. Schaumont, "Precomputation Methods for Hash-based Signatures on Energy-Harvesting Platforms" IEEE Transactions on Computers, 65(9):2925-2931, September 2016.
doi A. Aysu, E. Gulcan, D. Moriyama, P. Schaumont, "A Compact and Low-power ASIP Design for Lightweight PUF-based Authentication Protocols," IET Information Security, 10(5):232-241, August 2016.
doi N. F. Ghalaty, B. Yuce, P. Schaumont, "Analyzing the Efficiency of Biased-Fault Based Attacks," IEEE Embedded Systems Letters, 8(2):33-36, 2016. (extended version IACR ePrint 2015/663)
doi P. Schaumont, B. Yuce, K. Pabbuleti, D. Mane, "Secure Authentication with Energy-harvesting: A Multi-dimensional Balancing Act" Elsevier Journal on Sustainable Computing, Informatics and Systems, Special Issue on Disruptive Technologies for Energy Efficiency, 12:83-95, December 2016.
pdf video C. Patrick, P. Schaumont, "The Role of Energy in the Lightweight Cryptographic Profile," NIST 2nd Workshop on Lightweight Cryptography, Gaithersburg, MD, October 2016.
pdf C. Patrick, B. Yuce, N. Farhady Ghalaty, P. Schaumont, "Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy," Selected Areas in Cryptography (SAC 2016), St. John's, Canada, August 2016. (preprint on IACR ePrint 2016/850).
doi M. Taha, A. Reyhani-Masoleh, P. Schaumont, "Keymill: Side-Channel Resilient Key Generator," Selected Areas in Cryptography (SAC 2016), St. John's, Canada, August 2016. (preprint on IACR ePrint 2016/710). (DPA attack on IACR ePrint 2016/793).
doi B. Yuce, N. Farhady Ghalaty, H. Santapuri, C. Deshpande, C. Patrick, P. Schaumont, "Software Fault Resistance is Futile: Effective Single-glitch Attacks," Fault Diagnosis and Tolerance in Cryptography (FDTC 2016), Santa Barbara, CA, August 2016.
doi C. Deshpande, B. Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, L. Nazhandali, "A Configurable and Lightweight Timing Monitor for Fault Attack Detection," IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, PA, July 2016.
doi H. Rawat, P. Schaumont, "SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje," ACM Hardware and Architectural Support for Security and Privacy (HASP) 2016, Seoul, Korea, June 2016.
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B. Yuce, N. Farhady Ghalaty, C. Deshpande, C. Patrick, L. Nazhandali, P. Schaumont, "FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response," ACM Hardware and Architectural Support for Security and Privacy (HASP) 2016, Seoul, Korea, June 2016.
ieee A. Aysu, S. Gaddam, H. Mandadi, C. Pinto, L. Wegryn, P. Schaumont, "A Design Method for Remote Integrity Checking of Complex PCBs," Design, Automation & Test in Europe (DATE 2016), Dresden, Germany, March 2016.
pdf C. Patrick, B. Yuce, N. F. Ghalaty, P. Schaumont, "Lightweight Fault Attack Resistance in Software Using Intra-Instruction Redundancy," IACR ePrint Archive 2016/850.
pdf M. Taha, A. Reyhani-Masoleh, P. Schaumont "Keymill: Side-Channel Resilient Key Generator," IACR ePrint Archive 2016/710.
link S. Chong, J. Guttman, A. Datta, A. Myers, B. Pierce, P. Schaumont, T. Sherwood, N. Zeldovich, "Report on the NSF Workshop on Formal Methods for Security," arXiv:1608.00678 [cs.CR].
doi A. Aysu, P. Schaumont, "The Future of Real-Time Security: Latency-Optimized Lattice-Based Digital Signatures" ACM Transactions on Embedded Computing Systems, Special Issue on Embedded Platforms for Cryptography in the Coming Decade, 14(3), Article 43, April 2015 (18 pages).
doi A. Aysu, P. Schaumont, "Hardware/Software Co-design of Physical Unclonable Function based Authentications on FPGAs Microprocessors and Microsystems" Elsevier Microprocessors and Microsystems Journal, Special Issue on RECONFIG 2013, , April 2015 (9 pages).
doi H. Eldib, C. Wang, M. Taha, P. Schaumont, "Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 34(10):1558-568, April 2015 (11 pages).
eprint E. Gulcan, A. Aysu, P. Schaumont, "BitCryptor: Bit-Serialized Compact Crypto Engine on Reconfigurable Hardware" Indocrypt 2015, Bangalore, Inda, December 2015. Preprint version in IACR eprint 2015/744.
doi B. Yuce, N. Farhady Ghalaty, P. Schaumont, "Improving Fault Attacks on Embedded Software using RISC Pipeline Characterization" Fault Diagnosis and Tolerance in Cryptography (FDTC 2015), St Malo, France, September 2015.
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A. Aysu, E. Gulcan, D. Moriyama, P. Schaumont, M. Yung "End-to-end Design of a PUF based Privacy Preserving Authentication Protocol" Cryptographic Hardware and Embedded Systems (CHES 2015), St Malo, France, September 2015. Full version in IACR ePrint 2015/937.
doi N. F. Ghalaty, B. Yuce, P. Schaumont, "Differential Fault Intensity Analysis on PRESENT and LED Block Ciphers," sixth International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2015), LNCS 9064, 174-188, July 2015.
doi B. Yuce, N. F. Ghalaty, P. Schaumont, "TVVF: Estimating the Vulnerability of Hardware Cryptosystems against Timing Violation Attacks," IEEE International Symposium on Hardware Oriented Security and Trust (HOST-2015), 72-77, May 2015.
pdf A. Aysu, P. Schaumont, "Precomputation Methods for Faster and Greener Post-Quantum Cryptography on Emerging Embedded Platforms," IACR ePrint Archive 2015/255.
doi M. Taha, P. Schaumont, "Key-Updating for Leakage Resiliency with Application to AES Modes of Operation," IEEE Transactions on Information Forensics & Security, 10(3):519-528, March 2015.
doi H. Eldib, C. Wang, P. Schaumont, "Formal Verification of Software Countermeasures against Side-Channel Attacks," ACM Transactions on Software Engineering and Methodology, 24(2), December 2014.
doi A. Aysu, E. Gulcan, P. Schaumont, "SIMON Says, Break Area Records of Block Ciphers on FPGAs," IEEE Embedded Systems Letters, 6(2):37-40, April 2014.
doi J. Zhang, S. Iyer, X. Zheng, P. Schaumont, Y. Yang, "Hardware-software co-design for heterogeneous multiprocessor sensor nodes,", GLOBECOM 2014, 20-25, Austin, Texas, December 2014.
doi R. S. Chakraborty, V. Matyas, P. Schaumont, Patrick (Eds.), "Security, Privacy, and Applied Cryptography Engineering," 4th International Conference, SPACE 2014, Pune, India, October 18-22, 2014. Lecture Notes in Computer Science 8804, ISBN 978-3-319-12060-7.
doi E. Gulcan, A. Aysu, P. Schaumont, "A Flexible and Compact Hardware Architecture for the SIMON Block Cipher,", Third International Workshop on Lightweight Cryptography for Security & Privacy (LightSec 2014), Istanbul, Turkey, September 2014.
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N. F. Ghalaty, B. Yuce, M. Taha, P. Schaumont, "Differential Fault Intensity Analysis,", 11th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2014), Busan, Korea, September 2014.
doi K. Pabbuleti, D. Mane, P. Schaumont, "Energy Budget Analysis for Signature Protocols on a Self-Powered Wireless Sensor Node,", 10th Workshop on RFID Security (RFIDSec 2014), Oxford, UK, July 2014.
doi J. Zhang, Z. Pan, P. Schaumont, Y. Yang,"Application design and performance evaluation for multiprocessor sensor nodes,", 2014 IEEE Wireless Communications and Networking Conference (WCNC), 3272-3277, Istanbul, Turkey, April 2014.
doi H. Eldib, C. Wang, M. Taha and P. Schaumont, "QMS: Evaluating the side-channel resistance of masked software from source code", ACM/IEEE Design Automation Conference (DAC 14). San Francisco, CA, June 2014.
doi M. Taha and P. Schaumont, "Side-Channel Countermeasure for SHA-3 at Almost-Zero Area Overhead", IEEE Symposium on Hardware Oriented Security and Trust (HOST 2014), Arlington, VA, May 2014.
doi H. Eldib, C. Wang and P. Schaumont, "SMT-Based Verification of Software Countermeasures against Side-Channel Attacks", 20th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 14), Grenoble, France, April 2014.
doi N.F. Ghalaty, A. Aysu, P. Schaumont, "Analyzing and Eliminating the Causes of Fault Sensitivity Analysis", Design, Automation & Test in Europe (DATE 2014), Dresden, Germany, March 2014.
doi A. Maiti, P. Schaumont, "The Impact of Aging on a Physical Unclonable Function", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(9):1854-1864, August 2014.
doi Z. Chen, A. Sinha, P. Schaumont "Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks", IEEE Trans. Computers 62(1): 124-136 (2013).
doi A. Aysu, P. Schaumont, "PASC: Physically Authenticated Stable-Clocked SoC Platform on Low-Cost FPGAs", 2013 International Conference on Reconfigurable Computing and FPGAs, December 2013.
pdf M. Taha, P.Schaumont, "Differential Power Analysis of MAC-Keccak at Any Key-Length," 8th International Workshop on Security (IWSEC2013), Okinawa, Japan, November 2013.
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P. Schaumont, A. Aysu, "Three Design Dimensions of Secure Embedded Systems," Third International Conference on Security, Privacy, and Applied Cryptography Engineering(SPACE 2013), Kharagpur, India, October 2013.
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A. Aysu, N. Ghalaty, Z. Franklin, M. Yali, P. Schaumont "Digital Fingerprints for Low-Cost Platforms using MEMS sensors," 8th Workshop on Embedded Systems Security (WESS 2013), Montreal, Canada, September 2013.
pdf K. Pabbuleti, D. Mane, A. Desai, C. Albert, P. Schaumont, "SIMD Acceleration of Modular Arithmetic on Contemporary Embedded Platforms," 2013 IEEE High Performance Extreme Computing Conference (HPEC'13), Waltham, MA, September 2013.
pdf D. Mane, P. Schaumont, "Energy-Architecture Tuning for ECC-based RFID Tags", 9th Workshop on RFID Security (RFIDSec 2013), Graz, Austria, July 2013.
pdf A. Aysu, C. Patterson, P. Schaumont, "Low-Cost and Area-Efficient FPGA Implementations of Lattice Based Cryptography",IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2013), Austin, TX, June 2013.
pdf M. Taha, P. Schaumont, "Side-channel Analysis of MAC-Keccak",IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2013), Austin, TX, June 2013.
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P. Schaumont, I. Verbauwhede, "The Exponential Impact of Creativity on Computer-Engineering Education", International Conference on Micro-Electronic Systems Education 2013, Austin, TX, June 2013.
doi M. Srivastav, Y. Zuo, X. Guo, L. Nazhandali, P. Schaumont, "Study of ASIC Technology Impact Factors on Performance Evaluation of SHA-3 Candidates", 23rd Great Lakes Symposium on VLSI (GLSVLSI), Paris, France, May 2013.
pdf P. Schaumont, "Teaching Cyber-physical Systems in Layers", First Workshop on Cyber-Physical Systems Education (CPS-Ed 2013), Philadelpha, PA , April 2013.
P. Schaumont, "Embedded Authentication," Circuit Cellar Magazine #270, January 2013, 54-59.
P. Schaumont, "Chip Biometrics," Circuit Cellar Magazine #272, March 2013, 45-51.
P. Schaumont, "Dangerous Times," Circuit Cellar 25th Anniversary Issue, January 2013.
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M. Srivastav, X. Guo, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "Design and Benchmarking of an ASIC with Five SHA-3 Finalist Candidates," Elsevier Microprocessors and Microsystems - Embedded Hardware Design (Special Issue on "Digital System Security and Safety"), 2012.
doi A. Maiti, I. Kim and P. Schaumont, "A Robust Physical Unclonable Function with Enhanced Challenge-Response Set," IEEE Transactions on Information Forensics and Security, 7(1):333-345, February 2012.
pdf L. Judge, M. Cantrell, C. Kendir, P. Schaumont, "A Modular Testing Environment for Implementation Attacks," Workshop on Redefining and Integrating Security Engineering at ASE/IEEE International Conference on Cyber Security 12 (RISE), December 2012.
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M. Taha, P. Schaumont, "A Novel Profiled Attack in the Presence of High Algorithmic Noise," International Conference on Computer Design (ICCD 2012), September 2012.
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S. Mane, M. Taha, P. Schaumont, "Efficient and Side-Channel-Secure Block Cipher Implementation with Custom Instructions on FPGA," International Conference on Field Programmable Logic and Applications (FPL 2012), August 2012.
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A. Maiti, P. Schaumont, "A Novel Microprocessor-intrinsic Physical Unclonable Function," International Conference on Field Programmable Logic and Applications (FPL 2012), August 2012.
doi A. Maiti, V. Gunreddy, P. Schaumont, "A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions," Chapter 11 in "Embedded System Design with FPGAs," Eds. P. Athanas, D. Pnevmatikatos, N. Sklavos, Springer 2012, ISBN 978-1-4614-1361-5.
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J. Zhang, S. Iyer, P. Schaumont, Y. Yang, "Simulating Power/Energy Consumption of Sensor Nodes with Flexible Hardware in Wireless Networks," 9th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON), 2012.
pdf L. Judge, P. Schaumont, "A Flexible Hardware ECDLP Engine in Bluespec," Special-Purpose Hardware for Attacking Cryptographic Systems (SHARCS 2012), Washington, DC, March 2012.
pdf X. Guo, M. Srivistav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali, and P. Schaumont, "ASIC Implementations of Five SHA-3 Finalists," Design, Automation and Test in Europe (DATE2012), March 2012.
link P. Schaumont, "One-time Passwords from your Watch," Circuit Cellar Magazine #262, May 2012, 52-59.
P. Schaumont, "Electronic Signatures for Firmware Updates," Circuit Cellar Magazine #264, July 2012, 44-51.
P. Schaumont, "Hardware-accelerated Encryption," Circuit Cellar Magazine #266, September 2012, 48-57.
P. Schaumont, "True Random Number Generation," Circuit Cellar Magazine #268, November 2012, 52-59.
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Z. Chen, P. Schaumont, "A Parallel Implementation of Montgomery Multiplication on Multi-core Systems: Algorithm, Analysis, and Prototype," IEEE Transactions on Computers, 60(12):1692-1703, December 2011.
doi A. Maiti, P. Schaumont, "Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive," IACR Journal of Cryptology, Special Issue on Hardware and Security, 24(2):375-397, 2011.
pdf X. Guo, P. Schaumont, "The Technology Dependence of Lightweight Hash Implementation Cost", Ecrypt II 2011 Workshop on Lightweight Cryptography, November 2011.
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S. Mane, L. Judge, P. Schaumont, "An Integrated Prime-field ECDLP Hardware Accelerator with High-performance Modular Arithmetic Units," 2011 International Conference on Reconfigurable Computing and FPGAs (RECONFIG), December 2011.
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A. Maiti, L. McDougall and P. Schaumont, "The Impact of Aging on An FPGA-Based Physical Unclonable Function," 21st International Conference on Field Programmable Logic and Applications (FPL 2011), September 2011. Best Paper Award.
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X. Guo, Meeta Srivistav, S. Huang, D. Ganta, M. Henry, L. Nazhandali, and P. Schaumont, "Pre-silicon Characterization of NIST SHA-3 Final Round Candidates", 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2011), August 2011.
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S. Iyer, J. Zhang, Y. Yang, and P. Schaumont, "A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes," 2011 Electronic System Level Synthesis Conference, San Diego, June 2011.
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J. Zhang, Y. Tang, S. Hirve, S. Iyer, P. Schaumont, Y. Yang, "A Software-Hardware Emulator for Sensor Networks," 8th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks, June 2011. Best Paper Award.
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S. Morozov, C. Tergino, P. Schaumont, "System Integration of Elliptic Curve Cryptography on an OMAP Platform," 9th IEEE Symposium on Application Specific Processors, June 2011.
pdf X. Guo, M. Srivastav, S. Huang, D. Ganta, M. Henry, L. Nazhandali, P. Schaumont, "Silicon Implementation of SHA-3 Finalists: BLAKE, Groestl, JH, Keccak and Skein," ECRYPT II Hash Workshop 2011, May 2011.
pdf Z. Chen, X. Guo, A. Sinha, and P. Schaumont, "Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers" Design, Automation and Test in Europe (DATE2011), March 2011.
pdf A. Maiti, V. Gunreddy, P. Schaumont, "A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions", IACR ePrint 2011/657, November 2011.
pdf
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M. Gora, A. Maiti, P. Schaumont, "A Flexible Design Flow for Software IP Binding in FPGA," IEEE Transactions on Industrial Informatics, November 2010.
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X. Guo, P. Schaumont, "Optimized System-on-Chip Integration of a Programmable ECC Coprocessor," ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4(1), Article 6, December 2010.
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A. Sinha, Z. Chen, P. Schaumont, "A Comprehensive Analysis of Performance and Side-Channel Leakage of AES SBOX Implementations in Embedded Software," Fifth Workshop on Embedded Systems Security (WESS'2010), Scottsdale, AZ, October 2010.
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Z. Chen, A. Sinha, P. Schaumont, "Implementing Virtual Secure Circuit using a Custom-Instruction Approach," International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2010), Scottsdale, AZ, October 2010.
pdf X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations", NIST 2nd SHA-3 Candidate Conference, Santa Barbara, CA, August 2010.
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A. Maiti, J. Casarona, L. McHale, P. Schaumont "A Large Scale Characterization of RO-PUF," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, June 2010.
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J. Fan, X. Guo, E. De Mulder, P. Schaumont, B. Preneel, and I. Verbauwhede, "State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures," IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, June 2010.
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I. Kim, A. Maiti, L. Nazhandali, P. Schaumont, V. Vivekraja, H. Zhang, "From Statistics to Circuits: Foundations for Future Physical Unclonable Functions," chapter in "Towards Hardware Intrinsic Security," eds. A. Sadeghi, Springer Information Security and Cryptography Series, Part 1, 55-78, 2010, Springer.
pdf Z. Chen, P. Schaumont, "pSHS: A Scalable Parallel Software Implementation of Montgomery Multiplication for Multicore Systems," Design, Automation and Test in Europe (DATE 2010), March 2010.
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S. Morozov, A. Maiti, P. Schaumont, "A Comparative Analysis of Delay Based PUF Implementations on FPGA," 6th International Symposium on Applied Reconfigurable Computing, March 2010.
pdf X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings," IACR ePrint 2010/536, October 2010.
pdf X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations", NIST 2nd SHA-3 Candidate Conference, Santa Barbara, CA, August 2010.
pdf Z. Chen, P. Schaumont, "Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore," IACR ePrint Archive 2010/272, April 2010.
pdf S. Morozov, A. Maiti, P. Schaumont, "A Comparative Analysis of Delay Based PUF Implementations on FPGA," IACR ePrint Archive 2009/629, December 2009.
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X. Guo, J. Fan, P. Schaumont, I. Verbauwhede, "Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security,,"Proc. of the IACR Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009), September 2009.
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A. Maiti, P. Schaumont, "Improving the Quality of a Physical Unclonable Function using Configurable Ring Oscillators," 19th International Conference on Field Programmable Logic and Applications (FPL 2009), September 2009.
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Z. Chen, P. Schaumont, "Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting," Proc. IEEE Workshop on Hardware Oriented Security and Trust (HOST 2009), July 2009.
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M. Gora, A. Maiti, P. Schaumont, "A Flexible Design Flow for Software IP Binding in Commodity FPGA," IEEE Symposium on Industrial Embedded Systems (SIES 2009), July 2009.
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Z. Chen, P. Schaumont, "Side-channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects," 3th International Conference on Information Security and Assurance (ISA 2009), June 2009.
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Z. Chen, R. Nagesh, A. Reddy, P. Schaumont, "Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering," IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009), May 2009.
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A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function and True Random Number Generator: a Compact and Scalable Implementation," 19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009.
pdf X. Guo, P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage," Design, Automation and Test in Europe (DATE2009), April 2009.
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X. Guo, P. Schaumont, "Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform," 5th International Workshop on Applied Reconfigurable Computing (ARC2009), LNCS5453, pp. 169-180, Springer Verlag, March 2009.
doi A. Maiti, P. Schaumont, "Impact and Compensation of Correlated Process Variations on Ring Oscillator Based PUF," poster presentation, 17th International Symposium on Field Programmable Gate Arrays (FPGA 2009), February 2009.
P. Schaumont, "Engineering On-Chip Thermal Effects," Foundations for Forgery-Resilient Cryptographic Hardware, Eds. Guajardo J, Preneel B, Sadeghi A-R, Tuyls, Dagstuhl Seminar Report 2009.
pdf S. Morozov, A. Maiti, P. Schaumont, "A comparative analysis of delay based PUF implementations on FPGA," IACR ePrint Archive 2009/629, December 2009.
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doi
P. Schaumont, "A Senior Level Course in Hardware/Software Codesign," IEEE Transactions on Education, Special Issue on Micro-Electronic Systems Education, 51(3):306-311, August 2008.
pdf P. Schaumont, "Hardware/Software Codesign is a Starting Point in Embedded Systems Architecture Education",ARTIST Workshop on Embedded Systems Education (WESE 2008), October 2008
pdf Z. Chen, P. Schaumont, "Improving Secure Hardware Masking using an Equalization Technique", ACM Workshop on Embedded Systems Security (WESS 2008), October 2008.
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X. Guo, Z. Chen, P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
pdf
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M. Gora, E. Simpson, P. Schaumont, "Intellectual Property Protection for Embedded Sensor Nodes," International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
pdf
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Z. Chen, P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme", IEEE International Workshop on Hardware-Oriented Security and Trust, June 2008.
pdf
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P. Schaumont, K. Asanovic, J. Hoe, "MEMOCODE 2008 Co-Design Contest", Sixth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), June 2008.
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P. Schaumont, D. Hwang, "Turning Liabilities into Assets: Exploiting Deep-submicron CMOS Technology to Design Secure Embedded Circuits,", IEEE International Symposium on Circuits and Systems (ISCAS 08), May 2008, Seattle.
pdf Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms", ePrint IACR Archive, 2008/529, December 2008.
pdf Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms", ePrint IACR Archive, 2008/529, December 2008.
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P. Yu, P. Schaumont, "Secure FPGA Circuits using Controlled Placement and Routing," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), October 2007.
pdf
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P. Schaumont, K. Tiri, "Masking and Dual-Rail Logic Don't Add Up," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), September 2007.
pdf
doi
E. Simpson, P. Yu, P. Schaumont, S. Ahuja, S. Shukla, "VT Matrix Multiply Design for MEMOCODE 07," Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007), Nice, France.
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P. Schaumont, "A Senior Level course in hardware-software codesign," International Conference on Microelectronic Systems Education (MSE 2007), San Diego, June 2007.
pdf I. Verbauwhede, P. Schaumont, "Design Methods for Security and Trust," Design Automation and Test Conference in Europe (DATE 2007), Nice, France, April 2007.
pdf D. Ha, P. Schaumont, "Replacing Cryptography with Ultra Wideband (UWB) Modulation in Secure RFID," IEEE International Conference on RFID 2007, Grapevine, TX, March 2007.
pdf P. Schaumont, I. Verbauwhede, "Hardware/Software Codesign for Stream Ciphers," SASC (State of the Art of Stream Ciphers), Special workshop hosted by the ECRYPT Network of Excellence in Cryptology, Bochum, Germany, January 2007.
pdf
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P. Schaumont, D. Hwang, S. Yang, I. Verbauwhede, "Multi-level Design Validation in a Secure Embedded System," IEEE Transactions on Computers, special issue HLDVT 2005, October 2006.
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P. Schaumont, I. Verbauwhede, "A Component-based Design Environment for Electronic System-level Design," IEEE Design and Test of Computers, special issue on Electronic System-Level Design, 23(5), pp. 338-347, September-October 2006.
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D. Hwang, K. Tiri, A. Hodjat, B.C. Lai, S. Yang, P. Schaumont, I. Verbauwhede, "AES-Based Security Coprocessor IC in 0.18um CMOS with resistance to differential power analysis side-channel attacks," IEEE Journal of Solid-State Circuits, 41(4), April 2006.

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D. Hwang, P. Schaumont, K. Tiri, I. Verbauwhede, "Securing Embedded Systems," IEEE Security and Privacy Magazine, March-April 2006.

pdf
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E. Simpson, P. Schaumont, "Offline HW/SW Authentication for Reconfigurable Platforms," Workshop on Cryptographic Hardware and Embedded Systems 2006 (CHES 06), Yokohama, Japan, October 2006.
pdf
doi
P. Schaumont, D. Hwang, S. Yang, I. Verbauwhede, "Multi-level Design Validation in a Secure Embedded System," IEEE Transactions on Computers, special issue HLDVT 2005, October 2006.
pdf
doi
K. Tiri, P. Schaumont, "Changing the odds against masked logic," 13th Annual Workshop on Selected Areas in Cryptography, Montreal, Canada, 2006.
pdf
doi
B.C. Lai, P. Schaumont, W. Qin, I. Verbauwhede, "Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip," IEEE 17th INTERNATIONAL CONFERENCE ON Application-specific Systems, Architectures and Processors (ASAP), pp.15-18, Steamboat Springs, Colorado, September 2006.
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P. Yu, P. Schaumont, "Executing Hardware as Parallel Software for Picoblaze Networks," 16th International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006.
pdf P. Yu, P. Schaumont, D. Ha, "Securing RFID with Ultra-Wideband Modulation," 2nd Workshop on RFID Security (RFIDSec 2006), Graz, Austria, July 2006.
pdf H. Chan, P. Schaumont, I. Verbauwhede, "Process Isolation for Reconfigurable Hardware," 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, June 2006. (distinguished paper).
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K. Tiri, P. Schaumont, I. Verbauwhede, "Side-Channel Leakage Tolerant Architectures" third International Conference in Information Technology: New Generations (ITNG), Las Vegas, NV, April 2006.
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doi
I. Verbauwhede, K. Tiri, D. Hwang, and P. Schaumont, "Circuits and design techniques for secure ICs resistant to side-channel attack," International Conference on IC Design and Technology (ICICDT 2006).
pdf P. Schaumont, S. Shukla, I. Verbauwhede, "Design with race-free hardware semantics", 2006 Design Automation and Test in Europe (DATE) Conference, Munich, March 2006.
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D. Ching, P. Schaumont, and I. Verbauwhede, "Integrated modeling and generation of a reconfigurable network-on-chip," Int. J. Embedded Systems, Vol. 1, Nos. 3/4, 2005, p. 218-227.
pdf P. Schaumont, D. Hwang, I. Verbauwhede, "Platform-based design for an embedded fingerprint authentication device," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 24(12):1929-1936, December 2005.
pdf I. Verbauwhede, P. Schaumont, "Skiing the embedded systems mountain," ACM Transactions on Embedded Computing Systems (Special issue on embedded systems education), August 2005.
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D. Ching, P. Schaumont, and I. Verbauwhede, "Integrated modeling and generation of a reconfigurable network-on-chip," Int. J. Embedded Systems, Vol. 1, Nos. 3/4, 2005, p. 218-227.
pdf I. Verbauwhede, P. Schaumont, H. Kuo "Design and performance testing of a 2.29 Gb/s Rijndael Processor," IEEE Journal of Solid-State Circuits, pp. 569-572, March 2003.
doi P. Schaumont, I. Verbauwhede, "Domain-Specific Codesign for Embedded Security," IEEE COmputer 36(4):68-74, 2003.
pdf P. Schaumont, I. Verbauwhede, "ThumbPod puts security under your Thumb," Xilinx Xcell Online, Winter 2003.
pdf R. Pasko, L. Rynders, P. Schaumont, S. Vernalde, D. Durackova, "High Performance Flexible All-Digital Quadrature Up- and Down Converter Chip," IEEE Journal of Solid State Circuits, pp. 408-416, March 2001.
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L. Rynders, P. Schaumont, S. Vernalde, I. Bolsens, "High level analysis of clock regions in a C++ system description," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, December 2000, VE83A(N12):2631-2632
pdf R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, D. Durackova, "A new algorithm for Elimination of Common Subexpressions," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 18(1):58-68, January 1999.
pdf P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Low Power Digital Frequency Conversion Architectures," Kluwer Journal of VLSI Signal Processing, pp. 187-197, February 1998.
pdf P. Schaumont, B. Vanthournout, I. Bolsens, H. De Man, "Synthesis of Pipelined DSP accelerators with Dynamic Scheduling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5-1, pp. 59-68, March 1997.

pdf D. Hwang, P. Schaumont, S. Yang, I. Verbauwhede, "Multi-level Design Validation in a Secure Embedded System," Proceedings of the 2005 High Level Design and Validation Workshop, November 2005.
pdf B.C. Lai, P. Schaumont, I. Verbauwhede, "Energy and Performance Analysis of Mapping Parallel Multi-threaded Tasks for An On-Chip Multi-Processor System," IEEE International Conference on Computer Design (ICCD 2005), October 2005.
pdf B.C. Lai, P. Schaumont, I. Verbauwhede, "A Light-Weight Cooperative Multi-threading with Hardware Supported Thread-Management on an Embedded Multi-Processor System," Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, 2005, p. 1647-1651.
pdf S. Yang, P. Schaumont, and I. Verbauwhede, "Microcoded Coprocessor for Embedded Secure Biometric Authentication Systems," IEEE/ACM/IFIP International Conference on Hardware - Software Codesign and System Synthesis(CODES+ISSS'05), Sept. 2005.
pdf K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, "Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), August 2005.
pdf P. Schaumont, S. Shukla, and I. Verbauwhede, "Extended Abstract: A Race-free Hardware Modeling Language," Third ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2005), July 2005.
pdf K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, "AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-um CMOS Resistant to Side-Channel Power Analysis Attacks," 2005 Symposia on VLSI Technology and Circuits (VLSI SYMPOSIUM 2005), pp. 216-219, June 2005.
pdf P. Schaumont, B.C. Lai, W. Qin, I. Verbauwhede, "Cooperative multithreading on embedded multiprocessor architectures enables energy-scalable design," Proc. 2005 Design Automation Conference (DAC 2005), June 2005.
pdf K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang, P. Schaumont, I. Verbauwhede, "A Side-Channel Leakage Free Coprocessor IC in .18um CMOS for Embedded AES-Based Cryptographic and Biometric Processing," Proc. 2005 Design Automation Conference (DAC 2005), June 2005.
pdf O. Villa, P. Schaumont, I. Verbauwhede, M. Monchiero, G. Palermo, "Fast dynamic memory integration in co-simulation frameworks for multiprocessor system on-chip," Proc. Design Automation and Test Conference in Europe (DATE 2005), pp. 804-805, March 2005.
pdf H. Chan, P. Schaumont, I. Verbauwhede, "A secure multithreaded coprocessor interface," 3th Workshop on Optimizations for DSP and Embedded Systems, March 2005.
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B.C. Lai, P. Schaumont, and I. Verbauwhede, "CT-Bus: A heterogeneous CDMA/TDMA bus for future SOC," Proc. 38th Asilomar Conference on Signals, Systems, and Computers, November 2004.
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Y. Matsuoka, P. Schaumont, K. Tiri, and I. Verbauwhede, "Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques," Proc. Int. Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2004), pp. 303-311, September 2004.
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I. Verbauwhede, P. Schaumont, "The Happy Marriage of Architecture And Application in next-generation Reconfigurable Systems," ACM Computing Frontiers 2004, April 2004.
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P. Schaumont, K. Sakiyama, A. Hodjat, I. Verbauwhede, "Embedded software integration for coarse-grain reconfigurable architectures," 2004 Reconfigurable Architectures Workshop (RAW 2004), April 2004 errata

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D. Ching, P. Schaumont, I. Verbauwhede, "Integrated Modeling and Generation of A Reconfigurable Network-On-Chip," 2004 Reconfigurable Architectures Workshop (RAW 2004), April 2004.
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A. Hodjat, P. Schaumont, I. Verbauwhede, "Architectural design features of a programmable high throughput AES coprocessor," IEEE International Conference on Information Technology (ITCC 2004), April 2004.
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I. Verbauwhede, C. Piguet, P. Schaumont, B. Kienhuis, "Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia," 2004 Design Automation and Test in Europe (DATE 2004), February 2004.
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P. Schaumont, I. Verbauwhede, "Interactive cosimulation with partial evaluation," 2004 Design Automation and Test in Europe (DATE 2004), February 2004.

pdf P. Schaumont, K. Sakiyama, Y. Fan, D. Hwang, B. Lai, A. Hodjat, S. Yang, I. Verbauwhede, "Testing ThumbPod: softcore bugs are hard to find," IEEE International High Level Design Validation and Test Workshop (HLDVT), November 2003.
pdf D. Hwang, P. Schaumont, Y. Fan, A. Hodjat, B.C. Lai, K. Sakiyama, S. Yang, I. Verbauwhede, "Design flow for HW / SW acceleration transparency in the ThumbPod secure embedded system," 2003 Design Automation Conference, pp. 60-65, Los Angeles, June 2003.
pdf K. Sakiyama, P. Schaumont, D. Hwang, I. Verbauwhede, "Teaching trade-offs in system-level design methodologies," Proc. International COnference on Microelectronic Systems Education 2003 (MSE2003), pp. 64-65, June 2003.
pdf K. Sakiyama, P. Schaumont, I. Verbauwhede, "Finding the best system design flow for a high-speed JPEG encoder," Asia and South Pacific Design Automation Conference (ASP-DAC 2003), pp. 577-578, KitakYushu, Japan, January 2003.
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P. Schaumont, H. Kuo, I. Verbauwhede, "Unlocking the design secrets of a 2.29 Gb/s Rijndael encryption processor," 39th Design Automation Conference (DAC 2002), pp. 634-639, New Orleans, June 2002. Student Design Contest Winner, 1st place, operational category.
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H. Kuo, P. Schaumont, I. Verbauwhede, "A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 um CMOS technology.," 2002 IEEE Custom Integrated Circuits Conference (CICC), pp. 302-309, Orlando, May 2002.
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D. Desmet , P. Avasare , P. Coene , S. Decneut , F. Hendrickx , T. Marescaux , J. Mignolet , R. Pasko , P. Schaumont , D. Verkest "Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera," Embedded Processor Design Challenges : Systems, Architectures, Modeling, and Simulation - SAMOS, Lecture Notes on Computing Science (LNCS) 2268, April 2002.
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R. Pasko, S. Vernalde, P. Schaumont, "Techniques to evolve a C++ based system design language," Design, Automation and Test in Europe Conference and Exhibition (DATE 2002), pp. 302-309, March 2002.
pdf D. Verkest, P. Avasare, P. Coene, S. Decneut, D. Desmet, F. Hendrickx, T. Marescaux, J. Mignolet, P. Schaumont, R. Pasko, "Design of a Secure, Intelligent, and Reconfigurable Web Cam using a C Based System Design Flow," Asilomar 2001 Conference on Signals, Systems and Computers, pp. 463-467, Pacific Grove, CA, November 2001.
pdf P. Schaumont, I. Verbauwhede "A reconfiguration hierarchy for elliptic curve cryptography," Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, pp. 449-453, Pacific Grove, November 2001.
pdf F. Doucet, R. Gupta, M. Otsuka, P. Schaumont, S. Shukla, "Interoperability as a design issue in C++ based modeling environments," 14th International Symposium on System Synthesis, 2001, pp. 87-92, October 2001.
pdf Y. Ha, S. Vernalde, P. Schaumont, M. Engels, H. De Man, "Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects," International Conference on Parallel and Distributed Processing Techniques and Applications 2001 (PDPTA 2001), Las Vegas, June 2001.
pdf P. Schaumont, I. Verbauwhede, K. Keutzer, M. Sarrafzadeh, "A quick safari through the reconfiguration jungle," 38th Design Automation Conference (DAC 2001), pp. 172-177, Las Vegas, June 2001.
pdf R. Cmar, R. Pasko, J.-Y. Mignolet, G. Vanmeerbeeck, P. Schaumont, S. Vernalde, "Platform design approach for re-configurable network appliances," Custom Integrated Circuits, pp. 79-82, Orlando, May 2001.
pdf D. Verkest, W. Eberle, P. Schaumont, B. Gyselinckx, S. Vernalde "C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN," Custom Integrated Circuits Conference (CICC 2001), pp. 433-439, May 2001.
pdf G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Hardware/software partitioning of embedded system in OCAPI-xl," Proceedings of the Ninth International Symposium on Codesign (CODES), pp. 30-35, April 2001.
pdf Y. Ha, B. Mei, P. Schaumont, S. Vernalde, R. Lauwereins, H. De Man, "Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware," Proc. Field-Programmable Logic Conference 2001 (FPL 2001), pp. 264-274, Belfast, UK.
pdf Y. Ha, P. Schaumont, S. Vernalde, R. Lauwereins, H. De Man, "SW/HW Interface API for Java/FPGA Co-designed Applets," Proc. Field-Programmable Customg Computing Machines 2001 (FCCM 2001),
pdf Y. Ha, G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels, H. De Man, "Virtual Java/FPGA Interface for Networked Reconfiguration," Proc. ASP-DAC, pp. 558-563, Japan, January 2001.
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R. Pasko, R. Cmar, P. Schaumont, S. Vernalde, "Functional Verification of an Embedded Network Component by Co-Simulation with a Real Network," Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT00), pp. 64-67, Berkeley, CA, USA, November 2000.

pdf B. Mei, P. Schaumont, S. Vernalde, "A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems," Proc. PRORISC Workshop, Veldhoven, The Netherlands, November 2000.
pdf Y. Ha, P. Schaumont, M. Engels, S. Vernalde, F. Potargent, L. Rijnders, H. De Man, "A Hardware Virtual Machine to Support Networked Reconfiguration," Proc. IEEE International Workshop on Rapid System Prototyping (RSP00), p. 194-9, Paris, France, June 2000.
pdf R. Pasko, L. Rijnders, P. Schaumont, S. Vernalde, D. Durackova, "High Performance Flexible All-Digital Quadrature Up- and Down Converter Chip," Proc. IEEE Custom Integrated Circuits Conference (CICC00), pp. 43-46, Orlando, FL, USA, May 2000.
L. Rijnders, P. Schaumont, S. Vernalde, "High Level Clock Region Design of Digital Circuits," Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI00), Kyoto, Japan, April 2000.
pdf C. Lennard, P. Schaumont, G. de Jong, A. Haverinen, P. Hardee, "Standards for System-level Design: Practical Reality or Solution in Search of a Question ?," Hot Topic Session Proc. Design, Automation and Test in Europe (DATE00), pp. 90-96, Paris, France, March 2000.
pdf Y. Ha, P. Schaumont, L. Rijnders, S. Vernalde, F. Potargent, M. Engels, H. De Man, "A scalable architecture to support networked reconfiguration," Proc. PRORISC Workshop, pp. 677-83, Mierlo, The Netherlands, November 1999.
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P. Schaumont, R. Cmar, S. Vernalde, M. Engels, I. Bolsens, "Hardware Reuse at the Behavioral Level," Proc. Design Automation Conference (DAC99), pp. 784-789, New Orleans, CA, USA, June 1999, Nominated Best Paper.
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P. Schaumont, R. Cmar, S. Vernalde, M. Engels, "A 10 Mbit/s Upstream Cable Modem with Automatic Equalization," Proc. Design Automation Conference (DAC99), pp. 337-340, New Orleans, LA, USA, June 1999, Design Contest Finalist.
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S. Vernalde, P. Schaumont, I. Bolsens, "An Object Oriented Programming Approach for Hardware Design," Proc. IEEE Computer Society Workshop on VLSI, pp. 68-73, Orlando, FL, April 1999.
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R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, I. Bolsens, "A Methodology and Design Environment for DSP ASIC Fixed Point Refinement," Design, Automation and Test in Europe (DATE99), pp. 271-276, Munich, Germany, March 1999.
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P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, I. Bolsens, "A Programming Environment for the Design of Complex High Speed ASICs," Proc. Design Automation Conference (DAC98), pp. 315-320, San Francisco, CA, USA, June 1998.
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P. Schaumont, G. Vanmeerbeeck, E. Watzeels, S. Vernalde, M. Engels, I. Bolsens, "A Technique for Combined Virtual Prototyping and Hardware Design," Proc. IEEE International Workshop on Rapid System Prototyping (RSP98), pp. 156-161, Leuven, Belgium, June 1998.
pdf R. Pasko, P. Schaumont, V. Derudder, D. Durackova, "Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination," 10th International Symposium on System Synthesis (ISSS97), pp. 100-106, Antwerp, Belgium, September 1997.
pdf J. Maris, P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Dynamical analysis of all-digital symbol timing recovery in twisted pair broadband receivers," Digital Signal Processing Proceedings, 1997 (DSP 97), pp. 1055-1058, July 1997.
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P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Synthesis of Multi-Rate and Variable Rate Circuits for High Speed Telecommunications Applications," Proc. European Design and Test Conference (EDTC97), pp. 542-546, Paris, France, March 1997.
pdf P. Vandaele, M. Moonen, P. Schaumont, W. Trog, K. De Meyer, "Low Complexity Algorithms for Burstmode Communication in Upstream CATV networks," Proc. PRORISC Workshop, The Netherlands, November 1996.
pdf S. Vernalde, P. Schaumont, M. Engels, I. Bolsens, "Design Space Exploration of All-Digital Symbol Timing Adjustment Architectures," IEEE Fourth Symposium on Communications and Vehicular Technology in the Benelux, pp. 88-93, Gent, Belgium, October 1996.
pdf P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Digital Upconversion Architecture for Quadrature Modulators," IEEE Workshop on VLSI Signal Processing, pp. 315-324, San Francisco, CA, USA, October 1996.
pdf R. Lauwereins, M. Ade, P. Vandaele, M. Moonen, P. Schaumont, "Prototyping Quadrature Amplitude Modulation for Two-Way Communication on CATV networks," 7th Int. Conference on Signal Processing Applications and Technology ICSPAT, pp. 1570-1574, Boston, MA, USA, October 1996.
pdf P. Schaumont, B. Vanthournout, I. Bolsens and H. De Man, "Synthesis of Pipelined DSP accelerators with Dynamic Scheduling," Proc. International Symposium on System Synthesis (ISSS95), pp. 72-77, Cannes, 1995.

Presentations

"Lightning Talk: The Incredible Shrinking Black Box Model," 60th Design Automation Conference (DAC), San Francisco, July 2023.
"Building Cryptographic ASICs with Open-source Design Tools," Summer School on Real-world Crypto and Privacy, Vodice, Croatia, June 2023.
"Root-cause Analysis in Secure Hardware Design," 16th IEEE Dallas Circuits and Systems Conference, Denton, TX, April 2023.
"Tools and Methods for Pre-silicon Analysis of Secure Hardware," Summer School on Real World Cryptography, Sibenik, June 2022.
"Pre-silicon Side-channel Leakage Assessment with Architecture Correlation Analysis," Intel IPAS Tech Sharing, March 2022.
"Hardening Software against Implementation Attacks using Parallel Synchronous Programming," Future of Cryptographic Engineering Workshop, Sabanci Univeristy, June 2021.
"Security Aspects of Intermittent Computing," Dell EMC Seminar, May 2021.
"Hands-on Real-Time Digital Signal Processing using low-cost portable hardware," Texas Instruments University Program Webinar, March 2021. Also as ECEDHA Webinar, April 2021.
"Anticipating side-channel attacks on computer hardware, or why it's better to prepare than to repair," Cybercrime Lecture Series, Friedrich-Alexander-Universität Erlangen-Nürnberg, December 2020.
"EDA Tools for Security Testing and Countermeasure Synthesis," UK RISE Annual Conference 2020, November 2020.
"Electronic Design Automation for Side Channel Leakage Detection and Mitigation," Riscure User Workshop 2020, September 2020.
"Mitigation of Power-based Side-channel Leakage with Custom Firmware and Micro-Archiecture," RISC-V Security Working Group, September 2020.
"Fault Attacks on Embedded Software," Summer School on Real-world Cryptography and Privacy, Sibenik, Croatia, June 2019.
"Hardware Acceleration in Cryptography," Summer School on Real-world Cryptography and Privacy, Sibenik, Croatia, June 2019.
"Fault Attacks on Embedded Systems: Threats and Mitigation," Keynote talk at the DoD Anti-Tamper Conference, McLean, VA, April 2019.
"A Parallel Synchronous Model of Computation for Embedded Software," Universita della Svizzera Italiana, Lugano, March 2019.
"A Whitebox Introduction to Fault Attacks," Tutorial at 2018 Hardware Oriented Security and Trust (HOST 2018), McLean, VA, May 2018. (with Karine Heydemann, LIP6, and Qiaoyan Yu, UNH).
pdf "Fault Attacks on Embedded Software: Threats, Design, and Mitigation," Training School on Cryptanalysis of Ubiquitous Computing Systems, Ponta Delgada, Portugal, April 2018.
"Fault Aware Microprocessor Extension (FAME): From Concept to Prototype," Laboratoire d'Informatique de Paris 6 (LIP6), Paris, France, November 2017.
"Fault Attacks and their Mitigation in Embedded Processors," invited talk at International Test Conference 2017, Dallas, November 2017.
pdf "Cryptographic Hardware and Software," Postion statement at CICC 2017 Panel Hardware and Software Security: Gaps and Synergies, Austin, May 2017.
"Energy harvested security for the Internet of Things," I-SENSE, Florida Atlantic University, Boca Raton, December 2016.
pdf "Isolation for Security," Dagstuhl Seminar 16441 (Adaptive Isolation for Performance and Security), Wadern, November 2016.
video "Fault Injection as an Attack Vector against Trustworthy Embedded Systems," Georgia Tech Institute for Information Security and Privacy, Atlanta, October 2016.
pdf "Analyzing the Fault Injection Sensitivity of Secure Embedded Software," Qualcomm, San Diego, August 2016. Also presented at UCSD.
"FAME - Secure Software by a Fault-attack Aware Microprocessor Extension," QTech Seminar at TU Delft, Delft, Netherlands, July 2016.
pdf "SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje," ICIS Seminar at Radboud University, Nijmegen, Netherlands, July 2016.
"FAME, a Fault-attack Aware Microprocessor," ESAT/COSIC Seminar at KU Leuven, Leuven, Belgium, Januari 2016.
pdf "Challenges and Opportunities for Energy-Harvested Security," Workshop on Cryptography and Hardware Security for the Internet of Things, College Park, MD, October 2015.
"Experiments in Hardware Security with FPGA-based Microcontrollers," Okayama University, Okayama, JP, April 2015.
pdf "Threats and Countermeasures from Protocol to Secure Hardware Implementation," ASP-DAC 2015 Tutorial, Tokyo, JP, January 2015.
pdf "Current State of Design and Design Methods for Secure Hardware," Shonan NII Seminar on Design Methods for Secure Hardware, Shonan Village, JP, September 2014.
"Long-term Security from Fast-paced Technology," Xilinx Emerging Technology Symposium 2014, San Jose, CA, February 2014.
"Hardware/Software Co-design for Cryptography: Balancing Performance and Risk," Intel Software Professionals Conference 2013, Hillsboro, OR, October 2013.
pdf "Three Design Dimensions of Secure Embedded Systems," invited talk at Third International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE 2013), Kharagpur, India, October 2013.
pdf "Don't talk to strangers (without authentication)," CESCA Seminar, Virginia Tech, October 2013.
pdf "Authenticating Microcontrollers," Summer School on Design and Security of Cryptographic Functions, Algorithms and Devices, Albena, Bulgaria, July 2013.
pdf "Hardware Design for Cryptographers," Summer School on Design and Security of Cryptographic Functions, Algorithms and Devices, Albena, Bulgaria, July 2013.
"CPU Based Hardware Security," Qualcomm, San Diego, August 2012.
" Building Better Hardware for the Elliptic Curve Discrete Logarithm Problem," ECE Department Seminar at University of Connecticut, Storrs, CT, February 2012.
"Fault Attacks and Side Channel Analysis on Cryptographic Hardware," Guest Lecture at Prof. Burleson's Security Engineering class at University of Massachusetts, Amherst, MA, February 2012.
pdf "Moving PUFs out of the lab," COSIC Seminar at Katholieke Universiteit Leuven, February 2012. Also given as a CESCA seminar, February 2012.
pdf "Specialized Machines for Ccryptanalysis: 2 examples, 60 years apart," 2011 CESCA Seminar, VA, February 2011.
pdf "How to enjoy the variability of your FPGA," 2010 Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Wadern, Germany, July 2010.
"Trustworthy, High-Performance Cryptography on Embedded Multi-core Systems," 2010 Lockheed Martin Fellows Conference, Atlanta, GA, May 2010.
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"Secure Embedded Systems: A Software-Hardware Symbiosis," CS Department, Virginia Tech, April 2010.

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"Engineering On-chip Thermal Effects," Dagstuhl Seminar on Foundations for Forgery-resilient Cryptographic Hardware, Saarbrucken, Germany, July 2009.

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"Teaching Hardware/Software Codesign to the next generation of Computer Engineers", CS Department, University of California at Riverside, June 2008.
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"The embedded security challenge: Protecting bits-at-rest", 2007 ECE Department, George Mason University, June 2007.
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"Secure Design Methodology and the Tree of Trust" , 2007 ECRYPT Workshop on Secure Embedded Implementations, Friday workshop at the Design Automation and Test in Europe (DATE) Conference, Nice, France, 2007.
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"Secure Integration of Cryptographic Primitives", 2006 ECRYPT Summer School on Cryptographic Hardware, Side-channel, and Fault-attacks, Louvain-La-Neuve, Belgium, 2006.
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"System Level Design Methods for Secure Embedded Systems", 2005 Workshop on CRyptographic Advances in Secure Hardware (CRASH), Leuven, Belgium, 2005.
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"Hardware Platform Design and Evaluation using GEZEL", CSE Department, Penn State University, PA, 2005.
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"Challenges for the Logic Design of Secure Embedded Systems", 2005 Internal Workshop on Logic and Synthesis, Lake Arrowhead, CA, 2005.

Textbook

Book Cover Patrick Schaumont
Springer, 2nd Edition, 2012, xxii+480p
ISBN 978-1-4614-3736-9 (print)
ISBN 978-1-4614-3737-6 (online)
DOI 10.1007/978-1-4614-3737-6
December 2012

Order at Springer
Order at Amazon
Local site with Figures, Examples, Errata.

My favorite teaching topic is hardware/software codesign. It's a topic that goes to the core of computer engineering: How do we build efficient digital machines? Software programmers would say: by writing better code. Hardware designers would say: by building faster hardware. Codesigners know how to make the proper choice between the two.

More on this topic (teaching codesign):

pdf P. Schaumont, I. Verbauwhede, "The Exponential Impact of Creativity on Computer-Engineering Education", International Conference on Micro-Electronic Systems Education 2013, Austin, TX, June 2013.
pdf P. Schaumont, "Hardware/Software Codesign is a Starting Point in Embedded Systems Architecture Education," ARTIST Workshop on Embedded Systems Education (WESE 2008), October 2008.
pdf P. Schaumont, "A Senior Level Course in Hardware/Software Codesign," IEEE Transactions on Education, Special Issue on Micro-Electronic Systems Education, 51(3):306-311, August 2008.

Proceedings

doi C.H. Chang, D. E. Holcomb, F. Regazzoni, U. Rührmair, P. Schaumont (Eds), "Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop," ASHES@CCS 2020, Virtual Event, USA, November 13, 2020. ACM 2020, ISBN 978-1-4503-8090-4.
doi C.H. Chang, D. E. Holcomb, F. Regazzoni, U. Rührmair, P. Schaumont (Eds), "Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop," ASHES@CCS 2019, London, UK, November 15, 2019. ACM 2019, ISBN 978-1-4503-6839-1.
doi F. Regazzoni, P. Schaumont (Eds), "2017 Workshop on Fault Diagnosis and Tolerance in Cryptography," FDTC 2017, Taipei, Taiwan, September 25, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-2948-2.
doi S. Mangard, P. Schaumont (Eds), "Radio Frequency Identification: Security and Privacy Issues," 11th International Workshop, RFIDSEC 2015, New York City, New York, June 23-24, 2015. Lecture Notes in Computer Science 9440, Springer 2015, ISBN 978-3-319-24837-0.
doi R. S. Chakraborthy, V. Matyas, P. Schaumont (Eds), "Security, Privacy, and Applied Cryptography Engineering," 4th International Conference, SPACE 2014, Pune, India, October 18-22, 2014. Lecture Notes in Computer Science 8804, Springer 2014, ISBN 978-3-319-12060-7.
doi E. Prouff, P. Schaumont (Eds), "Cryptographic Hardware and Embedded Systems - CHES 2012 - 14th International Workshop," Lecture Notes in Computer Science 7428, Springer 2012, ISBN 978-3-642-33026-1.

Patents

T. Mousavirik, P. Schaumont, S. Tajik, “Electronic Tampering Detection," US Patent Application 20230401342-A1, 14 December 2023.
Y. Yao, B. Ege, P. Schaumont, T. Kathuria, "Side Channel Leakage Source Identification in an Electronic Design," WO Patent WO/2021/255019, 23 December 2021.
B. Yuce, N. F. Ghalaty, P. Schaumont, "Microprocessor Fault Detection and Response System," US Patent 10 452 493, 22 October 2019.
Y. Ha, P. Schaumont, M. Engels, S. Vernalde, "Virtual Hardware Machine, methods, and devices," US Patent 7 150 011, 12 December 2006.
P. Schaumont, R. Cmar, S. Vernalde, "Reuse of Hardware Components," US Patent 7 113 901, 26 September 2006.
P. Schaumont, S. Vernalde, J. Cox "A Design Environment and a Method for Generating an Implementable Description of a Digital System," US Patent 7 006 960, 28 February 2006.
P. Schaumont, S. Vernalde, M. Engeles, W. Trog, K. De Meyer, B. De Ceulaer, M. Moonen, P. Vandaele, "Head-end Receiver for a Tree Network," US Patent 6 584 147, 24 June 2003.

Editorials

doi P. Schaumont, "Emerging Computing Challenges in the Interaction of Hardware and Software" Computer 55(9): 4-5 (2022) Spotlight on Transactions, August 2022.
doi P. Schaumont, P. Montuschi, "Computer Security at the Forefront of Emerging Topics in Computing" Computer 54(9): 4-5 (2021) Spotlight on Transactions, August 2021.
doi C. H. Chang, D. E. Holcomb, U. Rührmair, P. Schaumont, "The ASHES 2019 special issue at JCEN" J. Cryptogr. Eng. 11(3): 199-200 (2021)
doi P. Schaumont, P. Montuschi, "The Rise of Hardware Security in Computer Architectures" IEEE Computer Magazine, Spotlight on Transactions, August 2018.
doi P. Schaumont, M. O'Neill, T. Güneysu, "Introduction for Embedded Platforms for Cryptography in the Coming Decade" ACM Transactions on Embedded Computing Systems, Special Issue on Embedded Platforms for Cryptography in the Coming Decade, 14(3), April 2015.
doi E. Prouff, P. Schaumont, "Introduction to the CHES 2012 special issue", Journal of Cryptographic Engineering, 3(1):1, Springer, 2013.
doi R.Bloem, P. Schaumont, "Guest Editorial," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Special Section on MEMOCODE 2009, 2010.
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P. Schaumont, A.K. Jones, S. Trimberger, "Guest Editors' Introduction to Security in Reconfigurable Systems Design," ACM Transactions on Reconfigurable Technology and Systems (TRETS), March 2009.
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P. Schaumont, A. Raghunathan, "Guest Editor's Introduction: Security and Trust in Embedded-Systems Design," IEEE Design and Test of Computers, Special Issue on Design and Test of ICs for Secure Embedded Computing, November/December 2007.