.. ECE 574

.. attention::

   This document was last updated |today|

.. _03systemverilog:

SystemVerilog
=============

.. important::

   The purpose of this lecture is as follows.

   * To review basic hardware modeling features of Verilog
   * To clarify innovations of SystemVerilog towards hardware modeling
   * To point out some of the more recent developments in HDL

.. attention::

   The following references are relevant background to this lecture.

   * Official Verilog-2001 Standard: `IEEE Std 1364-2001 <https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=954909>`_

   * Official SystemVerilog Standard: `IEEE Std 1800-2017 <https://ieeexplore.ieee.org/document/8299595>`_

   * J. Bachrach et al., "Chisel: Constructing hardware in a Scala embedded language," DAC Design Automation Conference 2012, San Francisco, CA, USA, 2012, pp. 1212-1221, `doi: 10.1145/2228360.2228584 <https://ieeexplore.ieee.org/document/6241660>`_.

   * S. Jiang, P. Pan, Y. Ou and C. Batten, "PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification," in IEEE Micro, vol. 40, no. 4, pp. 58-66, 1 July-Aug. 2020, `doi: 10.1109/MM.2020.2997638 <https://ieeexplore.ieee.org/document/9099625>`_.


Verilog
-------

Please refer to the slide deck :download:`PDF <pdf/lecture3-verilog.pdf>`

SystemVerilog
-------------

Please refer to the Cadence Course Materials on Canvas