General Information

  • CRN: 31151
  • Instructor: Patrick Schaumont (schaum@vt.edu)
    • Office: Durham 337
    • Office Hours: TR 2 PM - 3 PM
  • Class Meeting Times: TR 12:30 PM - 1:45 PM
  • Class Location: WLH 350
  • TA: Mohannad Ismail (imohannad@vt.edu)
    • Office: Durham 350
    • Office Hours: WF 1:30 PM - 2:30 PM
  • WWW:
    • Canvas is used for grade posting
    • Piazza is used as the discussion forum
    • Github is used to distribute and collect homework
    • CEL is where you can check out the DE1-SoC equipment

Objectives

This course discusses electronic system design at the boundary of hardware and software, considering applications that are realized partially in hardware and partially in software. This course covers modeling techniques of hardware and software components at different levels of abstraction and a study of interfacing techniques between hardware components and software components. The course includes homework and practical experiments. Having completed this course, you will have experience in the following.

  • Transform simple software programs into cycle-based hardware descriptions with equivalent behavior and vice versa;
  • Partition simple software programs into hardware and software components, and create appropriate hardware-software interfaces to reflect this partitioning;
  • Analyze and explain the control-flow and data-flow of a software program and a cycle-based hardware description;
  • Identify performance bottlenecks in a given hardware-software architecture and optimize them by transformations on hardware and software components;
  • Use simulation software to co-simulate software programs with cycle-based hardware descriptions.

Equipment and Design Software

  • Students will make use of the DE1-SoC Altera Design Kit by Terasic. This is a high-performance FPGA board equipped with a Cyclone V SoC Series device; it contains a dual core ARM A9 as well as an FPGA configurable fabric. Students will receive a loaner board, free-of-charge, for the duration of the course. The board must be returned to the department at the end of the semester. Students who fail to return their kit will receive an incomplete (I) grade. Instructions on how to obtain the DE1-SoC board will appear on the course website.

  • Students will make use of Altera Quartus Prime Lite Design Software, as well as the Altera SoC Embedded Design Software. This software needs to be installed on a laptop or workstation owned by the student. Quartus Prime includes FPGA design tools and Modelsim HDL simulation. The SoC EDS includes a toolchain for the ARM A9 cores on the FPGA. Installation instructions for this software will be published on the course website. If you have an older edition of this software on your computer, it’s a good idea to upgrade it. All assignments and design examples will be made assuming that you have access to Altera Quartus Prime Lite and Altera SoC EDS.

  • Students will need to have a GitHub account to download assignments and turn in solved problems. The course will make use of Github Classroom. Your student GitHub account should be connected to your vt.edu email in order to be recognized as an educational user.

Prerequisites

  • For undergraduate students, a grade of C- or better in each of
    • ECE 3534 (or ECE 2534), Microprocessor-based system design
    • ECE 3504 or ECE 3544, Digital Design I
  • I assume that the students in this course will have taken 3544, so that they have a working knowledge of the Verilog Hardware Description Language.
    • I do not recommend to take this course if you are completely unfamiliar with hardware design (ie. have never written a program in Verilog or VHDL before).
    • I do not recommend to take this course if you did not obtain at least C in a prerequisite course.
  • The course assumes the following abilities.
    • Knowledge of C programming, assembly programming;
    • Knowledge of basic hardware design concepts (Number systems, Combinational and Sequential logic, with applications such as counter modules and arithmetic operations in hardware);
    • Basic knowledge of Verilog, including the use of a simulator, and the use of a hardware synthesis tool;
    • The ability to undertake a substantial design project.

This course puts a great deal of emphasis on actual design and on learning-by-doing. Students have to be proactive and approach design problems in the same manner as a design engineer would approach them: by looking for a solution, by thinking before asking questions, by trying before giving up, and last but not least, by not giving up!

Text and References

  • This course will rely in part on the following textbook:

    Practical Introduction to Hardware/Software Codesign
    Patrick Schaumont
    Springer, 2nd Edition, 2013, xxii+480p
    ISBN 978-1-4614-3736-9 (print)
    ISBN 978-1-4614-3737-6 (online)
    DOI 10.1007/978-1-4614-3737-6

    Students at Virginia Tech can access the PDF of the book online on SpringerLink

    Please do not post or redistribute the PDFs.

  • An optional reference, also available on SpringerLink, is the following textbook. This reference is useful during the first few weeks of the course, when we cover the MSP430 Microcontroller.

    Introduction to Embedded Systems - Using Microcontrollers and the MSP430
    Manuel Jimenez, Rogelio Palomera, Isidoro Couvertier
    Springer, 2014, xxiii + 648p
    ISBN 978-1-4614-3143-5 (online)
    DOI 10.1007/978-1-4614-3143-5
    Students at Virginia Tech can access the PDF of the book online on SpringerLink

  • An optional reference is the following textbook. It is not
    available online, but the website contains many Verilog examples for
    design with the NIOS microcontroller.

    Embedded SoPC Design with Nios II Processor and Verilog Examples Pong Chu
    Wiley, 2012, 782p
    ISBN 978-1-118-01103-4 (print)

  • All hardware modeling will be done in Verilog. All software development will be for either the MSP430, the Nios-II, or else for the ARM A9 core.

  • Additional reading will be posted on the class website.

Assignments

  • There will be TBD homework assignments over the semester. The homework assignments will reinforce the class topics. They require development of programs in C and of hardware modules in Verilog, to construct systems with an FPGA design environment.

  • Near the end of the course, a ‘Codesign Challenge’ will be specified. This is a sample problem that combines all of the above experience in a single project. Students have about two weeks to solve it (Week 13 and Week 14). The results will be discussed in Week 15. A summary of assignments and results from the past years is available online.

  • The general policy for assignments is as follows:

    • Except for the Codesign Challenge, all assignments must be solved within one week. The turn-in schedule will be marked on the handout of each assignment.

    • There is no late policy in this course. Homework assignments have to be committed into the github repository before the due deadline of each assignment. No late policy means that late Homework gets a zero grade. The exceptions to this rule are described below under Special Needs.

    • Students are responsible to keep the course equipment (including the FPGA board, the laptop/workstation, and the design software) in good working condition. Technical issues are not a valid reason for a late turn-in.

    • All assignments are individual assignments and must be completed independently by the students. The Forum on the course web site can be used to discuss the assignments within the limits of the Honor Code Policy, provided below.

Grading

  • Semester grades will be based on the following weights.
Homework 40% of the points
Codesign Challenge 20% of the points
Exams (2 Midterms and a Final) 40% of the points

  • The exam dates are listed on the tentative schedule included in this syllabus. An exam may be exceptionally rescheduled for an individual student provided a valid reason has been approved by the instructor at least one week before the exam date.

  • Grading errors on assignments or exams can be appealed within one week after the graded assignment was returned to the student. Appeals must be made to the instructor.

Honor Code Policy

The Undergraduate Honor Code pledge that each member of the university community agrees to abide by states:

As a Hokie, I will conduct myself with honor and integrity at all times. I will not lie, cheat, or steal, nor will I accept the actions of those who do.

Students enrolled in this course are responsible for abiding by the Honor Code. A student who has doubts about how the Honor Code applies to an assignment is responsible for obtaining specific guidance from the course instructor before submitting the assignment for evaluation. Ignorance of the rules does not exclude any member of the University community from the requirements and expectations of the Honor Code.

Adherence to the Virginia Tech Honor Code is expected in all phases of this course. Any work that you submit for a grade must be your own. Violations will be reported to the Office of the Honor System.

  • It is a violation of the honor code to discuss explicit project solutions or exercise solutions.

  • All assignments are individual projects and must contain your own work. All external source code material used must be properly cited. It is a violation of the honor code to provide others access to ones’ own solution source code. It is also a violation to access other students’ solution files.

  • Midterm and Final are individual.

  • Virginia Tech provides additional information on the Undegraduate Honor System and on the Graduate Honor System.

Special Needs

  • Reasonable accommodations are available for students who have documentation of a disability from a qualified professional. Students should work through Services for Students with Disabilities (SSD) in 152 Henderson Hall. Any student with accommodations through the SSD Office should contact the instructor during the first two weeks of the semester.

  • If participation in some part of this class conflicts with your observation of specific religious holidays during the semester, please contact the instructor during the first two weeks of class to make alternative arrangements.

  • If you miss class due to illness, especially in the case of an exam or some deadline, see a professional in Schiffert Health Center. If deemed appropriate, documentation of your illness will be sent to the Dean’s Office for distribution to the instruction.

  • If you experience a personal or family emergency that necessitates missing class, contact the Dean of Students at 231-3787 or see them in 152 Henderson Hall.

Tentative Schedule

Week Date Class Topic
1 27 Aug X Class Intro (online)
  29 Aug C MSP430 Microcontroller
2 3 Sep C MSP430 Software Toolflow
  5 Sep C MSP430 Hardware Toolflow
3 10 Sep C MSP430 Perf Measurement
  12 Sep C MSP430 Mem Mapped Interface
4 17 Sep C Hardware/Software Communication
  19 Sep C MSP430 Coprocessor
5 24 Sep C Looking Back / Looking Forward
  26 Sep C Midterm I
6 1 Oct C HW/SW Synchronization
  3 Oct C Platform Designer
7 8 Oct C On-chip Bus I
  10 Oct C On-chip Bus II
8 15 Oct C Nios-II Custom Instructions
  17 Oct C Homework 5 Review
9 22 Oct C Dataflow
  24 Oct C Review Lecture
10 29 Oct X Midterm II
  31 Oct C FPGA-SoC I
11 5 Nov C FPGA-SoC II
  7 Nov C FPGA-SoC Coproc I
12 12 Nov C FPGA-SoC Coproc II
  14 Nov C FPGA-SoC Profiling and Debugging
13 19 Nov C Codesign Challenge I
  21 Nov C Codesign Challenge II
  26 Nov X Thanksgiving Holiday
  28 Nov X Thanksgiving Holiday
14 3 Dec X TBD
  5 Dec X TBD
15 10 Dec C Codesign Results
  12 Dec X Reading Day

X = class does not meet
C = class does meet