Introduction

Homework 1 is a Verilog simulation of an MSP430 based application, along with some performance analysis. Before you can start the homework, you need to complete the software installation of the design tools required for this course. Consult the instructions in the software installation instructions.

This homework makes use of Github Classroom to distribute and collect assignments. You will need to turn in your homework by pushing your answers (in the format specified at the end of the homework) onto your homework repository. The turn-in time of your homework is the timestamp of the latest commit in your homework repository.

Preparation: Download the assignment from Github Classroom

  • In order to create your repository for this homework, log in to github.com.
  • Collect the GitHub Classroom link for homework 1, and post it into a browser.
  • Accept the homework invitation. This will lead to the creation of a private repository https://github.com/vt-ece4530-f19/homework-1-user, where ‘user’ will be replaced by your github account name.
  • Open a Cygwin window and change to directory /home/local (create it if it does not exist). Download the starter files of the homework to your laptop with the command
git clone https://github.com/vt-ece4530-f19/homework-1-user

where you replace user with your github account name.

If you are new to git, take a moment to learn the basic concepts of working with a version control system. The following are the bare minimum set of commands.

  • To add a file to your local repository, use git add FILE, with FILE a file or directory. You use the same command to mark a file for being part of the next version commit (aka staging a change).
  • To commit your current working version to the local repository use git commit -m "COMMENT", with COMMENT a descriptive string.
  • To turn in a version of your homework, use git push. You can push as many times as you like until the deadline. If you push into your GitHub repository after the deadline, your homework is considered late.

Configuring openmsp430 for simulation

In hands-on homework such as this one, there will always be some effort required from your side, in order to understand what is going on, and in order to succeed. You will need to familiarize yourself with the openmsp430 environment, the msp-430 cross-gcc compiler, Cygwin, and Quartus. This is an expected effort in this course - consulting manuals, doing experiments, and so forth. It is integral part of the modern design process. You can ask questions on the Discussions board regarding the tools we’re going to use.

When you navigate to your local copy of the homework, you will find the following materials.

  • openmsp430: The RTL (Register Transfer Level) of the openmsp430 core
  • portops: A software application for the openmsp430 core

First, study the directory layout of openmsp430. The following subdirectories are important.

  • doc/openMSP430.pdf contains the design manual for openmsp430. Reading this manual will significantly help your understanding of the openmsp430 core. Refer to it as often as needed.

  • core/rtl/verilog contains the Verilog description for openmsp430 core. This design includes the microcontroller core, without memories (ROM/RAM).

  • core/bench/verilog contains the testbench of the openmsp430 core.

  • core/sim/rtl_sim/run contains scripts to run simulations.

  • core/sim/rtl_sim/src-c contains C test programs for the openmsp430.

Configure the simulator

We will use the modelsim simulator. Edit the simulation script for C programs in sim/rtl_sim/run/run_c. Specifically edit the OMSP_SIMULATOR environment variable to select vsim (Modelsim).

Configure the MSP430 core

The C test programs assume a core of 24K program memory and 16 K data memory. The openmsp430 comes with a configuration file, openMSP430_defines.v. Open that configuration file in an editor an select the memory configuration indicated above (24K program, 16K data).

Test the simulation

Run the sandbox test program in core/sim/rtl_sim/run.

./run_c sandbox

If you have configured everything well, you will see the following output.

$ ./run_c sandbox
Cleanup...
 =======================================================
| Start simulation:             sandbox
 =======================================================
dos2unix: converting file pmem.sh to Unix format...
Compile, link & generate IHEX file (Program Memory: 24576 B, Data Memory: 16384 B, Peripheral Space: 512 B)...
rm -f sandbox sandbox.a43 sandbox.lst sandbox.elf sandbox.size *.o mylib/*.o
msp430-elf-gcc -D PFX_MSP430_ELF -O2 -Wall -g -mcpu=msp430 -mhwmult=none   -c -o main.o main.c
msp430-elf-gcc -D PFX_MSP430_ELF -O2 -Wall -g -mcpu=msp430 -mhwmult=none   -c -o mylib/copydata.o mylib/copydata.c
msp430-elf-gcc -D PFX_MSP430_ELF -O2 -Wall -g -mcpu=msp430 -mhwmult=none -T linker.msp430-elf.x -o sandbox.elf main.o mylib/copydata.o
msp430-elf-objcopy -O ihex sandbox.elf sandbox.a43
msp430-elf-objdump -dSt sandbox.elf >sandbox.lst
msp430-elf-size  sandbox.elf >sandbox.size
Convert ELF file to IHEX format...
Convert IHEX file to Verilog MEMH format...
Start Verilog simulation...
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
Start time: 20:40:38 on Aug 31,2019
vlog "+acc=prn" -f ../src/submit.f "+define+SEED=0" "+define+NO_DMA_VERIF" -R -c -do "run -all"
-- Compiling module tb_openMSP430
-- Compiling module ram
-- Compiling module io_cell
...

Top level modules:
        tb_openMSP430
        omsp_dbg_i2c
        omsp_dbg_hwbrk
        omsp_clock_mux
Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.5b

# vsim -lib work -c -do "run -all" tb_openMSP430 omsp_dbg_i2c omsp_dbg_hwbrk omsp_clock_mux
# Loading work.tb_openMSP430
# Loading work.ram
# Loading work.openMSP430
...
# run -all
#  ===============================================
# |                 START SIMULATION              |
#  ===============================================
#  ===============================================
# |               SIMULATION DONE                 |
# |       (stopped through verilog stimulus)      |
#  ===============================================
# ** Note: $finish    : stimulus.v(84)
#    Time: 151300 ns  Iteration: 1  Instance: /tb_openMSP430
# End time: 20:40:42 on Aug 31,2019, Elapsed time: 0:00:04
# Errors: 0, Warnings: 0

Question 1: portops (10 points)

Your first task will be to study the portops program and simulate it on openmsp430.

You have to develop a Verilog testbench for this program. The testbench needs to follow the following conventions, in order to be usable by the simulation scripts:

  • It needs to be called portops.v.
  • It needs to reside in the same directory as the C code.

The easiest is to study the sandbox example, and in particular the sandbox.v Verilog testbench. Your testbench, for portops.v, has the following requirements.

  • The testbench needs to drive the input of port P1 permanently to the value 0xE5.
  • The testbench needs to monitor any changes on the output of port P2, and print the new value as well as a timestamp that shows when the new value took effect. Consult the Verilog command $monitor if you are unsure how to do this.
  • The testbench needs to simulate 5,000 clock cycles. Then, it needs to end the simulation.

Once you have developed this testbench portops.v, you can run the Verilog simulation with

./run_c portops

The simulation finishes without showing output waveforms. However, if you have programmed the testbench correctly, you should see something as follows. Note that I have obfuscated the output value appearing on port P2; you will have to deliver the correct answer in reponse to this homework question.

$ ./run_c portops
Cleanup...
 =======================================================
| Start simulation:             portops
 =======================================================
dos2unix: converting file pmem.sh to Unix format...
Compile, link & generate IHEX file (Program Memory: 24576 B, Data Memory: 16384 B, Peripheral Space: 512 B)...
rm -f portops portops.a43 portops.lst portops.elf *.o *~
/cygdrive/c/ti/msp430-gcc/bin/msp430-elf-gcc  -Wall -mmcu=msp430c1111 -c main.c -o portops.o
/cygdrive/c/ti/msp430-gcc/bin/msp430-elf-gcc -mmcu=msp430c1111 -T linker.msp430.x portops.o -o portops.elf
/cygdrive/c/ti/msp430-gcc/bin/msp430-elf-size portops.elf
   text    data     bss     dec     hex filename
    140       4       4     148      94 portops.elf
/cygdrive/c/ti/msp430-gcc/bin/msp430-elf-objcopy -O ihex portops.elf portops.a43
/cygdrive/c/ti/msp430-gcc/bin/msp430-elf-objdump -dSt portops.elf >portops.lst
Convert ELF file to IHEX format...
Convert IHEX file to Verilog MEMH format...
Start Verilog simulation...
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
Start time: 20:52:07 on Aug 31,2019
vlog "+acc=prn" -f ../src/submit.f "+define+SEED=0" "+define+NO_DMA_VERIF" -R -c -do "run -all"
-- Compiling module tb_openMSP430
-- Compiling module ram
...

Top level modules:
        tb_openMSP430
        omsp_dbg_i2c
        omsp_dbg_hwbrk
        omsp_clock_mux
Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.5b

# vsim -lib work -c -do "run -all" tb_openMSP430 omsp_dbg_i2c omsp_dbg_hwbrk omsp_clock_mux
# Loading work.tb_openMSP430
# Loading work.ram
# Loading work.openMSP430
...
# run -all
#  ===============================================
# |                 START SIMULATION              |
#  ===============================================
# t= 300 P2=00
#
# t=14550 P2=...
#
#  ===============================================
# |               SIMULATION DONE                 |
# |       (stopped through verilog stimulus)      |
#  ===============================================
# ** Note: $finish    : stimulus.v(44)
#    Time: 250300 ns  Iteration: 1  Instance: /tb_openMSP430
# End time: 20:52:14 on Aug 31,2019, Elapsed time: 0:00:07
# Errors: 0, Warnings: 0

You need produce a listing that shows the Verilog testbench you wrote, as well as the output of the Verilog simulation, showing the proper value for P2 and the time when this value was reached.

Question 2: Performance (10 points)

In this question, we will relate the software program instructions to the modelsim waveform viewer window.

You can run the Modelsim simulation on the portops example of the first question as follows. After completing Question 1, you will note there’s a work directory in the core/sim/rtl_sim/run directory.

Open Modelsim, then select File - Change Directory and navigate to this run directory. In the Modelsim library window you will see a work directory. Then, click Simulate - Start Simulation, and select the work/tb_openMSP430 entity to simulate.

To complete this question, you will have to select a few signals to observe in the waveform viewer window. You are free to choose what signals, as long as they lead you to the correct answer.

Consider again the C program portops/main.c. Assume that you’re using the same testbench as in Question 1.

  • Part 1: How many clock cycles does a single execution of the function cnt take to complete? You will count the number of clock cycles from the first clock cycle of the first instruction of cnt, until the last clock cycle of the last instruction of cnt. Note that cnt has a data-dependent execution time. The answer to this question relates to the very first invocation of cnt for the specific testbench used in this assignment.

  • Part 2: How many clock cycles does it take for the C statement if (a \& 0x1) r = r + 1; to finish, when the if-condition is true? You will count the number of clock cycles from the first instruction related to the evaluation of this if-statement, to the last clock cycle of the last instruction of this if-statement. Note that we are specifically looking for the case when the if-statement is true, that is, when r = r + 1 executes. You will have to monitor the simulation carefully to identify this case.

To answer this question, you’ll need to make use of Modelsim, as well as of the listing files provided by the C compiler. You will also make use of your knowledge in micro-controller architectures.

  • Hint: The file portops.lst contains the dissassembled executable listing.

  • Hint2: The MSP430 program counter is register R0. It’s inside of the MSP430 structural hierarchy.

  • Hint3: The address of the program memory starts from 0x0, but in the MSP430 address space, the program memory is mapped to address 0xA000. Furthermore, the program memory address is counted in words, while the MSP430 address space is counted in bytes.

You need to screen-capture a waveform window that shows the start of the execution of the cnt function. Make sure that the starting address is clearly visible in the waveform viewer window. Explain which signals you have included in the waveform viewer window.

You also need to provide a cycle count number for Part 1 and Part 2. Keep in mind that this question is on 10 points; if you give a binary answer (such as ‘Part 1: 250 clock cycles’), then you can expect a binary grading (such as ‘Wrong - 0 points’). If you want partial grading, you will have to include additional details on your reasoning to determine the proper amount of clock cycles for each Part.

What to turn in

  • Add your portops simulation directory in openmsp430/core/sim/rtl-sim/src-c to your homework repository.
git add portops
  • Create PDF document with your answer to Question 1 and 2. The only acceptable format is PDF. Word files and text files will be returned ungraded.

Include your name on top of the first page of the PDF. Under your name, include the statement: “I confirm that all the solutions in this Homework are my own.

  • Add the PDF document to the repository at root level. The file name of the document is hw1_username.pdf with username your github User Name.
git add hw1_username.pdf
  • Commit the changes to your local repository, and push back the local repository to GitHub. Note that the timestamp of the git push on github counts as your Homework turn-in time.
git commit -m 'Homework 1 result'
git push

Good Luck!